SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 10

• Manufacturer Part Number: SAM9X25
• Manufacturer: Atmel Corporation

Specifications of SAM9X25

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 2
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

4.2.1
10
SAM9X25
Reset State
When “Reset State” is mentioned, the configuration is defined by the “Reset State” column of the
Pin Description table.
In the tables that follow, the column “Reset State” indicates the reset state of the line with
mnemonics.
Indicates whether the PIO Line resets in I/O mode or in peripheral mode. If “PIO” is mentioned,
the PIO Line is maintained in a static state as soon as the reset is released. As a result, the bit
corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low.
If a signal name is mentioned in the “Reset State” column, the PIO Line is assigned to this func-
tion and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling
memories, in particular the address lines, which require the pin to be driven as soon as the reset
is released.
Indicates whether the signal is input or output state.
Indicates whether Pull-Up, Pull-Down or nothing is enabled.
Table 4-2.
• “PIO” “/” signal
• “I”/”O”
• “PU”/”PD”
GPIO_CLK2
GPIO_CLK
GPIO_ANA
RSTJTAG
EBI_CLK
I/O Type
USBFS
USBHS
CLOCK
EBI_O
SYSC
GPIO
VBG
DIB
EBI
I/O Frequency
SAM9X25 I/O Type Assignment and Frequency
(MHz)
0.25
0.25
133
133
480
40
54
75
25
66
10
12
50
25
Charge Load
50 (3.3V)
30 (1.8V)
50 (3.3V)
30 (1.8V)
(pF)
10
10
10
10
10
10
10
10
10
10
50
25
40mA (peak)
Current
Output
16mA,
all Address and control lines (output only) except the
NRST, NTRST, BMS, TCK, TDI, TMS, TDO, RTCK
HFSDPA, HFSDPB/DFSDP, HFSDPC, HFSDMA,
all Data lines (Input/output) except the following
MCI0CK, MCI1CK, SPI0SPCK, SPI1SPCK,
HHSDPA, HHSDPB/DHSDP, HHSDMA,
WKUP, SHDN, JTAGSEL, TST, SHDN
all PIO lines except the following
HFSDMB/DFSDM, HFSDMC
XIN, XOUT, XIN32, XOUT32
EMACx_ETXCK, ISI_MCK
HHSDMB/DHSDM
Signal Name
ADx, GPADx
DIBN, DIBP
following
CK, #CK
VBG
11054AS–ATARM–29-Jul-11