SAM9X25 Atmel Corporation, SAM9X25 Datasheet
SAM9X25
Specifications of SAM9X25
Related parts for SAM9X25
SAM9X25 Summary of contents
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... Individually Programmable Open-drain, Pull-up and pull-down resistor, Synchronous Output • Package – 217-ball BGA, pitch 0.8 mm ® Processor running 400 MHz @ 1.0V +/- 10% AT91SAM ARM-based Embedded MPU SAM9X25 Summary NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com. 11054AS–ATARM–29-Jul-11 ...
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... The External Bus Interface incorporates controllers for 8-bank DDR2/LPDDR, SDRAM/LPS- DRAM, static memories, and specific circuitry for MLC/SLC NAND Flash with integrated ECC. The SAM9X25 is available in a 217-ball BGA package with 0.8mm ball pitch. SAM9X25 2 11054AS–ATARM–29-Jul-11 ...
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... Block Diagram Figure 2-1. SAM9X25 Block Diagram 11054AS–ATARM–29-Jul-11 PIO PIO SAM9X25 3 ...
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... Fast Interrupt Input PA0-PA31 Parallel IO Controller A PB0-PB18 Parallel IO Controller B PC0-PC31 Parallel IO Controller C PD0-PD21 Parallel IO Controller D SAM9X25 4 gives details on the signal names classified by peripheral. Clocks, Oscillators and PLLs Shutdown, Wakeup Logic ICE and JTAG Reset/Test Debug Unit - DBGU Advanced Interrupt Controller - AIC ...
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... Multimedia Card 0 Slot A Data MCI1_DA0-MCI1_DA3 Multimedia Card 1 Slot A Data 11054AS–ATARM–29-Jul-11 External Bus Interface - EBI Static Memory Controller - SMC NAND Flash Support DDR2/SDRAM/LPDDR Controller High Speed MultiMedia Card Interface - HSMCI0-1 SAM9X25 Type Active Level I/O I/O Output Input Low Output Low ...
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... SPI Serial Clock SPIx_NPCS0 SPI Peripheral Chip Select 0 SPIx_NPCS1-SPIx_NPCS3 SPI Peripheral Chip Select TWDx Two-wire Serial Data TWCKx Two-wire Serial Clock SAM9X25 6 Universal Asynchronous Receiver Transmitter - UARTx Synchronous Serial Controller - SSC Timer/Counter - TCx x=0..5 Serial Peripheral Interface - SPIx Two-Wire Interface -TWIx Type Active Level ...
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... CRSDV Receive Data Valid 11054AS–ATARM–29-Jul-11 Pulse Width Modulation Controller- PWMC USB Host High Speed Port - UHPHS USB Device High Speed Port - UDPHS Ethernet 10/100 - EMAC0 RMII Ethernet 10/100 - EMAC1 SAM9X25 Type Active Level Output Analog Analog Analog Analog ...
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... Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference CANRXx CAN input CANTXx CAN output DIBN Soft Modem Signal DIBP Soft Modem Signal SAM9X25 8 Analog-to-Digital Converter - ADC CAN Controller - CANx Soft Modem - SMD Type Active Level Input Input Output I/O Analog Input ...
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... Package and Pinout The SAM9X25 is available in 217-ball BGA package. 4.1 Overview of the 217-ball BGA Package Figure 4-1 Figure 4-1. 4.2 I/O Description Table 4-1. I/O Type GPIO GPIO_CLK GPIO_CLK2 GPIO_ANA EBI EBI_O EBI_CLK RSTJTAG SYSC VBG USBFS USBHS CLOCK DIB 11054AS–ATARM–29-Jul-11 shows the orientation of the 217-ball BGA Package. ...
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... Indicates whether the signal is input or output state. • “PU”/”PD” Indicates whether Pull-Up, Pull-Down or nothing is enabled. SAM9X25 10 SAM9X25 I/O Type Assignment and Frequency I/O Frequency Charge Load Output (MHz) (pF) Current 40 ...
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... The PB18 “Reset State” column shows “PIO, I, PU, ST”. That means the line PIO18 is configured as an Input with Pull-Up and Schmitt Trigger enabled. PD14 reset state is “PIO, I, PU”. That means PIO Input with Pull-Up. PD15 reset state is “A20, O, PD” which means output address line 20 with Pull-Down. SAM9X25 11 ...
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... PB0 D4 VDDANA GPIO PB1 D2 VDDANA GPIO PB2 E4 VDDANA GPIO PB3 D1 VDDANA GPIO_CLK PB4 E3 VDDANA GPIO PB5 B3 VDDANA GPIO_ANA PB6 C2 VDDANA GPIO_ANA PB7 SAM9X25 12 Primary Alternate PIO Peripheral A Dir Signal Dir Signal I/O TXD0 I/O RXD0 I/O RTS0 I/O CTS0 I/O SCK0 I/O TXD1 I/O RXD1 I/O TXD2 I/O RXD2 I/O DRXD ...
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... I/O PC2 I/O PC3 I/O PC4 I/O PC5 I/O PC6 I/O PC7 I/O PC8 I/O PC9 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O FIQ SAM9X25 PIO Peripheral B PIO Peripheral C Dir Signal Dir Signal O O PCK1 O O PCK0 O O PWM0 O O PWM1 O I PWM2 O I PWM3 ADTRG I TWD1 TWCK1 TIOA3 TIOB3 TCLK3 TIOA4 TIOB4 ...
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... POWER VDDPLLA T13 VDDOSC POWER VDDOSC U13 GNDOSC GND GNDOSC H14, K8, VDDCORE POWER VDDCORE K9 H8, J8, GNDCORE GND GNDCORE K10 U16 VDDUTMII POWER VDDUTMII SAM9X25 14 Primary Alternate PIO Peripheral A Dir Signal Dir Signal I/O NANDOE I/O NANDWE I/O A21/NANDALE I/O A22/NANDCLE I/O NCS3 I/O NWAIT I/O D16 I/O D17 I/O D18 ...
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... BA0 O A17 O BA1 O A18 O BA2 O A19 SDCS O NRD O O NWRE O O NBS1 O SAM9X25 PIO Peripheral B PIO Peripheral C Dir Signal Dir Signal Reset State Signal, Dir, PU, Dir PD ...
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... RSTJTAG RTCK P10 VDDIOP0 RSTJTAG NRST T11 VDDIOP0 RSTJTAG NTRST A6 VDDBU CLOCK XIN32 A5 VDDBU CLOCK XOUT32 T12 VDDOSC CLOCK XIN U12 VDDOSC CLOCK XOUT SAM9X25 16 Primary Alternate PIO Peripheral A Dir Signal Dir Signal O NBS3/DQM3 I/O I I/O DFSDP ...
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... Power Considerations 5.1 Power Supplies The SAM9X25 has several types of power supply pins. Table 5-1. SAM9X25 Power Supplies Name Voltage Range, nominal VDDCORE 0.9-1.1V, 1.0V 1.65-1.95V, 1.8V VDDIOM 3.0-3.6V, 3.3V 1.65-1.95V, 1.8V VDDNF 3.0-3.6V, 3.3V VDDIOP0 1.65-3.6V VDDIOP1 1.65-3.6V VDDBU 1.65-3.6V VDDUTMIC 0.9-1.1V, 1.0V VDDUTMII 3.0-3.6V, 3.3V VDDPLLA 0.9-1.1V, 1.0V VDDOSC 1.65-3.6V VDDANA 3.0-3.6V, 3.3V Note: 1. Refer to Table 4-2 for more details. 11054AS–ATARM–29-Jul-11 ...
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... Separate Masters for both instruction and data access providing complete Matrix – Separate Address and Data Buses for both the 32-bit instruction interface and the – On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit SAM9X25 18 each quarter of the page ...
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... APB/AHB bridge The AT91SAM9X25 product embeds two separated APB/AHB bridges. This architecture enables to make concurrent access on both bridge. Each peripheral can be clocked at a lower speed (MCK divided clock) in order to decrease the current consumption. 6.3 Bus Matrix • 12-layer Matrix, handling requests from 11 masters • ...
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... Master 2&3 Master 4&5 Master 6 Master 7 Master 8 Master 9 Master 10 Master 11 6.5 Matrix Slaves The Bus Matrix of the AT91SAM9X25 product manages 9 slaves. Each slave has its own arbi- ter, allowing a different arbitration per slave. Table 6-2. Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 Slave 5 Slave 6 Slave 7 ...
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... All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the USB Device High speed DMA to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and shown as “-” in the following table. AT91SAM9X25 Master to Slave Access Table 6-3. Masters ...
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... USB The AT91SAM9X25 features the following USB communication ports: • 2 Hosts (A and B) High Speed (EHCI) and Full Speed (OHCI) • 1 Host (C) Full Speed only (OHCI) • 1 Device High Speed The High Speed USB Host Port A is shared with the High Speed USB Device port and con- nected to the second UTMI transceiver ...
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... SPI0 SPI0 USART0 USART0 USART1 USART1 TWI0 TWI0 TWI2 TWI2 UART0 UART0 SSC SSC 11054AS–ATARM–29-Jul-11 DMA Channel Definition DMA Channel HW T/R interface Number RX/ SAM9X25 Table 23 ...
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... The hardware interface numbers are also given in 6-5. Table 6-5. Instance name HSMCI1 SPI1 SPI1 SMD SMD TWI1 TWI1 ADC DBGU DBGU UART1 UART1 USART2 USART2 USART3 USART3 SAM9X25 24 DMA Channel Definition DMA Channel HW T/R interface Number RX/ ...
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... Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug Unit – Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins. 11054AS–ATARM–29-Jul-11 SAM9X25 25 ...
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... Memories Figure 7-1. SAM9X25 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256 MBytes 0x0FFF FFFF 0x1000 0000 EBI 256 MBytes Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI Chip Select 1 256 MBytes DDR2/LPDDR SDR/LPSDR 0x2FFF FFFF 0x3000 0000 EBI 256 MBytes ...
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... Embedded Memories 7.2.1 Internal SRAM The SAM9X25 embeds a total of 32 Kbytes of high-speed SRAM. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0030 0000. After Remap, the SRAM also becomes available at address 0x0. 7.2.2 Internal ROM The SAM9X25 embeds an Internal ROM, which contains the SAM-BA program ...
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... SDRAM Power-up Initialization by Software • CAS Latency Supported • Auto Precharge Command Not Used • SDR-SDRAM with 16-bit Datapath and Eight Columns Not Supported – Clock Frequency Change in Precharge Power-down Mode Not Supported SAM9X25 28 Average Latency of Transactions) 11054AS–ATARM–29-Jul-11 ...
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... System Controller can be addressed from a single pointer by using the stan- dard ARM instruction set, as the Load/Store instruction have an indexing mode of ±4 KBytes. Figure 8-1 on page 30 Figure 7-1 on page 26 peripherals. 11054AS–ATARM–29-Jul-11 shows the System Controller block diagram. shows the mapping of the User Interface of the System Controller SAM9X25 29 ...
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... Figure 8-1. SAM9X25 System Controller Block Diagram periph_irq[2..30] pit_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset SHDN WKUP XIN32 SLOW CLOCK XOUT32 OSC 12M RC XIN 12MHz MAIN OSC XOUT UPLL PLLA periph_nreset periph_nreset periph_clk[2..3] PA0-PA31 ...
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... Chip ID: 0x819A_05A1 • Chip ID Extension: 4 • JTAG ID: 0x05B2_F03F • ARM926 TAP ID: 0x0792_603F 8.2 Backup Section The SAM9X25 features a Backup Section that embeds: • RC Oscillator • Slow Clock Oscillator • Real Time Counter (RTC) • Shutdown Controller • 4 Backup Registers • Slow Clock Control Register (SCKCR) • ...
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... SAM9X25 32 Figure 7-1, the Peripherals are mapped in the upper 256 Mbytes of the address defines the Peripheral Identifiers of the SAM9X25. A peripheral identifier is required Peripheral Identifiers Instance Name Instance Description AIC Advanced Interrupt Controller SYS System Controller Interrupt PIOA,PIOB Parallel I/O Controller A and B ...
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... Peripheral Signal Multiplexing on I/O Lines The SAM9X25 features 4 PIO Controllers, PIOA, PIOB, PIOC and PIOD, which multiplex the I/O lines of the peripheral set. Each PIO Controller controls 32 lines, 19 lines, 32 lines and 22 lines respectively for PIOA, PIOB, PIOC and PIOD. Each line can be assigned to one of three peripheral functions Refer to 11054AS– ...
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... Asynchronous Mode stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection SAM9X25 34 peripherals Sensors and data per chip select ...
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... Two UARTs • Independent receiver and transmitter with a common programmable Baud Rate Generator • Even, Odd, Mark or Space Parity Generation • Parity, Framing and Overrun Error Detection • Automatic Echo, Local Loopback and Remote Loopback Channel Modes 11054AS–ATARM–29-Jul-11 SAM9X25 35 ...
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... Compatibility with MMC Plus Specification Version 4.3 • Compatibility with MultiMedia Card Specification Version 4.1 • Compatibility with SD Memory Card Specification Version 2.0 • Compatibility with SDIO Specification Version V2.0. • Compatibility with CE ATA SAM9X25 TDM Buses, Magnetic Card Reader, ...) 11054AS–ATARM–29-Jul-11 ...
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... External trigger pin – Timer Counter outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all • Compare level interrupt for background signal surveillance 11054AS–ATARM–29-Jul-11 enabled channels SAM9X25 37 ...
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... Gather support for extracting fields from a system memory area into a contiguous – User enabled auto-reloading of source, destination and control registers from initially – Auto-loading of source, destination and control registers from system memory at end SAM9X25 38 lists transfer. Writing a stream of data into non-contiguous fields in system memory ...
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... Low Power Mode and Programmable Wake-up on Bus Activity or by the Application • Data, Remote, Error and Overload Frame Handling 11054AS–ATARM–29-Jul-11 to control the flow of a DMA transfer in place of a hardware handshaking interface completion, Single/Multiple transaction completion or Error condition SAM9X25 39 ...
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... Type I Caller ID (CID) decoding • Sixty-three embedded and upgradeable country profiles • Embedded AT commands • SmartDAA – Extension pick-up detection – Digital line protection – Line reversal detection – Line-in-use detection – Remote hang-up detection – Worldwide compliance SAM9X25 40 11054AS–ATARM–29-Jul-11 ...
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... Mechanical Overview Figure 11-1. 217-ball BGA Package Drawing 11054AS–ATARM–29-Jul-11 SAM9X25 41 ...
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... Device and 217-ball BGA Package Maximum Weight 450 Table 11-2. 217-ball BGA Package Characteristics Moisture Sensitivity Level Table 11-3. Package Reference JEDEC Drawing Reference JESD97 Classification Table 11-4. Soldering Information Ball Land Solder Mask Opening SAM9X25 MO-205 e1 0.43 mm ± 0.05 0.30 mm ± 0.05 11054AS–ATARM–29-Jul-11 ...
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... SAM9X25 Ordering Information Table 12-1. SAM9X25 Ordering Information Ordering Code AT91SAM9X25-CU 11054AS–ATARM–29-Jul-11 Package Package Type BGA217 Green SAM9X25 Temperature Operating Range Industrial -40°C to 85°C 43 ...
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... SAM9X25 44 11054AS–ATARM–29-Jul-11 ...
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