SAM3N4A Atmel Corporation, SAM3N4A Datasheet - Page 459

• Manufacturer Part Number: SAM3N4A
• Manufacturer: Atmel Corporation

Specifications of SAM3N4A

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 24
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

• BITS: Bits Per Transfer
(See the
The BITS field determines the number of data bits transferred. Reserved values should not be used.
• SCBR: Serial Clock Baud Rate
In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The
Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud
rate:
Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.
Note:
• DLYBS: Delay Before SPCK
This field defines the delay from NPCS valid to the first valid SPCK transition.
When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.
Otherwise, the following equations determine the delay:
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
Value
10
11
12
13
14
15
16
If one of the SCBR fields inSPI_CSRx is set to 1, the other SCBR fields in SPI_CSRx must be set to 1 as well, if they are
required to process transfers. If they are not used to transfer data, they can be set at any value.
0
1
2
3
4
5
6
7
8
(Note:)
below the register table;
Name
8_BIT
9_BIT
10_BIT
11_BIT
12_BIT
13_BIT
14_BIT
15_BIT
16_BIT
–
–
–
–
–
–
–
Delay Before SPCK
SPCK Baudrate
Section 27.8.9 “SPI Chip Select Register” on page
=
Description
8_bits for transfer
9_bits for transfer
8_bits for transfer
8_bits for transfer
8_bits for transfer
8_bits for transfer
8_bits for transfer
8_bits for transfer
8_bits for transfer
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
-------------- -
SCBR
MCK
=
DLYBS
------------------ -
MCK
458.)
SAM3N
SAM3N
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