ATmega649A Atmel Corporation, ATmega649A Datasheet - Page 271
ATmega649A
Manufacturer Part Number
ATmega649A
Description
Manufacturer
Atmel Corporation
Specifications of ATmega649A
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Segment Lcd
100
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Table 26-4.
Note:
8284D–AVR–6/11
Signal
Name
NEGSEL_2
NEGSEL_1
NEGSEL_0
PASSEN
PRECH
SCTEST
ST
VCCREN
1. Incorrect setting of the switches in
several input choices to the S&H circuitry on the negative input of the output comparator in
path is selected from either one ADC pin, Bandgap reference source, or Ground.
Boundary-scan Signals for the ADC
Direction as
seen
from the ADC
Input
Input
Input
Input
Input
Input
Input
Input
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P
If the ADC is not to be used during scan, the recommended input values from
be used. The user is recommended not to use the differential amplifier during scan. Switch-Cap
based differential amplifier require fast operation and accurate timing which is difficult to obtain
when used in a scan chain. Details concerning operations of the differential amplifier is therefore
not provided.
The AVR ADC is based on the analog circuitry shown in
sive approximation algorithm implemented in the digital logic. When used in Boundary-scan, the
problem is usually to ensure that an applied analog voltage is measured within some limits. This
can easily be done without running a successive approximation algorithm: apply the lower limit
on the digital DAC[9:0] lines, make sure the output from the comparator is low, then apply the
upper limit on the digital DAC[9:0] lines, and verify the output from the comparator to be high.
The ADC need not be used for pure connectivity testing, since all analog inputs are shared with
a digital port pin as well.
When using the ADC, remember the following
• The port pin for the ADC channel in use must be configured to be an input with pull-up disabled
• In Normal mode, a dummy conversion (consisting of 10 comparisons) is performed when
to avoid signal contention.
enabling the ADC. The user is advised to wait at least 200ns after enabling the ADC before
controlling/observing any ADC signal, or perform a dummy conversion before using the first
result.
Description
Input Mux for negative input for differential
signal, bit 2
Input Mux for negative input for differential
signal, bit 1
Input Mux for negative input for differential
signal, bit 0
Enable pass-gate of differential amplifier.
Precharge output latch of comparator.
(Active low)
Switch-cap TEST enable. Output from
differential amplifier send out to Port Pin
having ADC_4
Output of differential amplifier will settle
faster if this signal is high first two ACLK
periods after AMPEN goes high.
Selects Vcc as the ACC reference voltage.
Figure 26-8 on page 269
(1)
(Continued)
will make signal contention and may damage the part. There are
Recommende
d Input when
not in use
0
0
0
1
0
0
0
1
Figure 26-8 on page 269
Output Values when
recommended inputs are
used, and CPU is not using the
ADC
Figure
26-8. Make sure only one
Table 26-4
0
0
0
1
1
0
0
0
with a succes-
should
271
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