AT83C5135 Atmel Corporation, AT83C5135 Datasheet - Page 16

• Manufacturer Part Number: AT83C5135
• Manufacturer: Atmel Corporation

Specifications of AT83C5135

• Max. Operating Frequency: 32 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Sram (kbytes): 1.25
• Eeprom (bytes): 512
• Operating Voltage (vcc): 2.7 to 3.6
• Timers: 4
• Mask Rom (kbytes): 16
• Watchdog: Yes

6.4
16
Registers
AT83C5134/35/36
Table 6-2.
Reset Value = 0000 0000b
Bit Number
TWIX2
7
7
6
5
4
3
2
1
0
Oscillator Frequency
32 MHz
40 MHz
Mnemonic
CKCON0 (S:8Fh)
Clock Control Register 0
PCAX2
TWIX2
WDX2
WDX2
T2X2
T1X2
T0X2
SIX2
Bit
X2
6
Description
TWI Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit
has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Watchdog Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit
has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Programmable Counter Array Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit
has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Enhanced UART Clock (Mode 0 and 2)
This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit
has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer2 Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit
has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer1 Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit
has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer0 Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit
has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
System Clock Control bit
Clear to select 12 clock periods per machine cycle (STD mode, F
Set to select 6 clock periods per machine cycle (X2 mode, F
PCAX2
5
R+1
12
3
SIX2
4
T2X2
3
N+1
10
2
T1X2
2
CPU =
T0X2
CPU
F
PLLDIV
1
PER =
B9h
21h
= F
F
7683C–USB–11/07
PER =
OSC
).
F
OSC
X2
0
/
2).