AT83C5135 Atmel Corporation, AT83C5135 Datasheet - Page 118
AT83C5135
Manufacturer Part Number
AT83C5135
Description
Manufacturer
Atmel Corporation
Datasheet
1.AT83C5134.pdf
(166 pages)
Specifications of AT83C5135
Max. Operating Frequency
32 MHz
Cpu
8051-12C
Max I/o Pins
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
1
Sram (kbytes)
1.25
Eeprom (bytes)
512
Operating Voltage (vcc)
2.7 to 3.6
Timers
4
Mask Rom (kbytes)
16
Watchdog
Yes
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21.10.2
118
AT83C5134/35/36
USB Interrupt Control System
Table 21-2.
As shown in Figure 21-16, many events can produce a USB interrupt:
• TXCMPL: Transmitted In Data (see
• RXOUTB0: Received Out Data Bank 0 (see
• RXOUTB1: Received Out Data Bank 1 (only for Ping-pong endpoints) (see
• RXSETUP: Received Setup (see
• STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints) (see
• SOFINT: Start of Frame Interrupt
• WUPCPU: Wake-Up CPU Interrupt
• SPINT: Suspend Interrupt
when the Host accept a In packet.
hardware when an Out packet is accepted by the endpoint and stored in bank 0.
page
stored in bank 1.
an SETUP packet is accepted by the endpoint.
125). This bit is set by hardware when a STALL handshake has been sent as requested by
STALLRQ, and is reset by hardware when a SETUP packet is received.
Interrupt Enable Register” on page
Frame packet has been received.
Interrupt Enable Register” on page
detected on the USB bus, after a SUSPEND state.
Enable Register” on page
on the USB bus.
125). This bit is set by hardware when an Out packet is accepted by the endpoint and
IPHUSB
0
0
1
1
Priority Levels
122.). This bit is set by hardware when a USB suspend is detected
(See “USBIEN Register USBIEN (S:BEh) USB Global Interrupt
IPLUSB
(See “USBIEN Register USBIEN (S:BEh) USB Global
Table 21-9 on page
0
1
0
1
122.). This bit is set by hardware when a USB Start of
122.). This bit is set by hardware when a USB resume is
(See “USBIEN Register USBIEN (S:BEh) USB Global
Table 21-9 on page
Table 21-9 on page
USB Priority Level
0
1
2
3
Lowest
Highest
125). This bit is set by hardware when
125). This bit is set by hardware
125). This bit is set by
Table 21-9 on page
Table 21-9 on
7683C–USB–11/07
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