AT32UC3A3256 Atmel Corporation, AT32UC3A3256 Datasheet - Page 532

• Manufacturer Part Number: AT32UC3A3256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.9.6
Name:
Access Type:
Offset:
Reset value:
• FSLENHI: Transmit Frame Sync Length High Part
• FSEDGE: Transmit Frame Sync Edge Detection
• FSDEN: Transmit Frame Sync Data Enable
• FSOS: Transmit Frame Sync Output Selection
• FSLEN: Transmit Frame Sync Length
32072G–11/2011
FSDEN
MSBF
FSEDGE
31
23
15
Others
FSOS
7
-
The four MSB of the FSLEN field.
Determines which edge on Frame Sync will generate the SR.TXSYN interrupt.
1: TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.
0: The TX_DATA line is driven with the default value during the Transmit Frame Sync signal.
This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the TSHR register if
TFMR.FSDEN is equal to one.
Note: The four most significant bits for this field are located in the FSLENHI field.
0
1
2
3
4
5
0
1
Transmit Frame Mode Register
Selected Transmit Frame Sync Signal
None
Negative Pulse
Positive Pulse
Driven Low during data transfer
Driven High during data transfer
Toggling at each start of data transfer
Reserved
30
22
14
Frame Sync Edge Detection
Positive Edge Detection
Negative Edge Detection
6
-
-
TFMR
Read/Write
0x1C
0x00000000
FSLENHI
DATDEF
FSOS
29
21
13
5
-
28
20
12
4
-
27
19
11
TX_FRAME_SYNC Pin
3
-
Undefined
Input-only
Output
Output
Output
Output
Output
DATLEN
26
18
10
2
-
DATNB
FSLEN
25
17
9
1
-
FSEDGE
24
16
8
0
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