AT32UC3A3256 Atmel Corporation, AT32UC3A3256 Datasheet - Page 313

• Manufacturer Part Number: AT32UC3A3256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

18.8
18.8.1
32072G–11/2011
Module Configuration
DMA Handshake Signals
The specific configuration for the PDCA instance is listed in the following tables.
Table 18-6.
Table 18-7.
The table below defines the valid Peripheral Identifiers (PIDs). The direction is specified as
observed from the memory, so RX means transfers from peripheral to memory and TX means
from memory to peripheral.
Table 18-8.
Features
Number of channels
Register
PSRn
VERSION
PID Value
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PDCA Configuration
Register Reset Values
PDCA Handshake Signals
Reset Value
n
0x00000110
Direction
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
TX
TX
TX
TX
TX
TX
TX
TX
TX
PDCA
8
Peripheral Instance
ADC
SSC
USART0
USART1
USART2
USART3
TWIM0
TWIM1
TWIS0
TWIS1
SPI1
SSC
USART0
USART1
USART2
USART3
SPI0
TWIM0
TWIM1
TWIS0
TWIS1
Peripheral Register
CDRx
RHR
RHR
RHR
RHR
RHR
RHR
RHR
RHR
RHR
RDR
RDR
THR
THR
THR
THR
THR
THR
THR
THR
THR
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