ISD5116PY Nuvoton Technology Corporation of America, ISD5116PY Datasheet - Page 23

• Manufacturer Part Number: ISD5116PY
• Description: IC VOICE REC/PLAY 8-16MN 28-DIP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: ISD5100r

Specifications of ISD5116PY

• Interface: I²C
• Filter Pass Band: 1.7 ~ 3.4kHz
• Duration: 8 ~ 16 Min
• Mounting Type: Through Hole
• Package / Case: 28-DIP (0.600", 15.24mm)
• For Use With: ISD-ES511 - EVALUATION SYSTEM FOR ISD5100ISD-ES501 - EVALUATION SYSTEM FOR ISD5008
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

To select this mode, the following control bits must be configured in the ISD5100 Series configuration
registers. To set up the transmit path:
To set up the receive path:
The status of the rest of the functions in the ISD5100 Series chip must be defined before the con-
figuration registers settings are updated:
1. Select the FTHRU path through the ANA OUT MUX—Bits AOS0, AOS1 and AOS2 control the
2. Power up the ANA OUT amplifier—Bit AOPD controls the power up state of ANA OUT. This is
1. Set up the ANA IN amplifier for the correct gain—Bits AIG0 and AIG1 control the gain settings
2. Power up the ANA IN amplifier—Bit AIPD controls the power up state of ANA IN. This is bit
3. Select the ANA IN path through the OUTPUT MUX—Bits OPS0 and OPS1 control the state of
4. Power up the Speaker Amplifier—Bits OPA0 and OPA1 control the state of the Speaker and
1. Power down the Volume Control Element — Bit VLPD controls the power up state of the
2. Power down the AUX IN amplifier — Bit AXPD controls the power up state of the AUX IN input
3. Power down the SUM1 and SUM2 Mixer amplifiers — Bits S1M0 and S1M1 control the SUM1
4. Power down the FILTER stage — Bit FLPD controls the power up state of the FILTER stage in
5. Power down the AGC amplifier — Bit AGPD controls the power up state of the AGC amplifier.
state of the ANA OUT MUX. These are the D6, D7 and D8 bits respectively of Configuration
Register 0 (CFG0) and they should all be ZERO to select the FTHRU path.
bit D5 of CFG0 and it should be a ZERO to power up the amplifier.
of this amplifier. These are bits D14 and D15 respectively of CFG0. The input level at this pin
determines the setting of this gain stage. The
36 will help determine this setting. In this example, we will assume that the peak signal never
goes above 1 volt p-p single ended. That would enable us to use the 9 dB attenuation setting,
or where D14 is ONE and D15 is ZERO.
D13 of CFG0 and should be a ZERO to power up the amplifier.
the OUTPUT MUX. These are bits D3 and D4 respectively of CFG0 and they should be set to
the state where D3 is ONE and D4 is ZERO to select the ANA IN path.
AUX amplifiers. These are bits D1 and D2 respectively of CFG0. They should be set to the
state where D1 is ONE and D2 is ZERO. This powers up the Speaker Amplifier and
configures it for its higher gain setting for use with a piezo speaker element and also powers
down the AUX output stage.
Volume Control. This is bit D0 of CFG0 and it should be set to a ONE to power down this
stage.
amplifier. This is bit D10 of CFG0 and it should be set to a ONE to power down this stage.
mixer and bits S2M0 and S2M1 control the SUM2 mixer. These are bits D7 and D8 in CFG1
and bits D5 and D6 in CFG1 respectively. All 4 bits should be set to a ONE to power down
these two amplifiers.
the device. This is bit D1 in CFG1 and should be set to a ONE to power down the stage.
This is bit D0 in CFG1 and should be set to a ONE to power down this stage.
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ANA IN Amplifier Gain Settings table
Publication Release Date: Oct 31, 2008
ISD5100 SERIES
Revision 1.42
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