SC16IS750IPW-T NXP Semiconductors, SC16IS750IPW-T Datasheet - Page 47

• Manufacturer Part Number: SC16IS750IPW-T
• Description: IC UART I2C/SPI 24-TSSOP
• Manufacturer: NXP Semiconductors

Specifications of SC16IS750IPW-T

• Features: Low Current
• Number Of Channels: 1, UART
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP (0.173", 4.40mm Width)
• For Use With: 568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
14. Dynamic characteristics
Table 37.
All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;
V
an input voltage of V
[1]
[2]
[3]
[4]
SC16IS740_750_760_6
Product data sheet
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SCL
BUF
HD;STA
SU;STA
SU;STO
HD;DAT
VD;ACK
VD;DAT
SU;DAT
LOW
HIGH
f
r
SP
d1
d2
d3
d4
d5
d6
d7
d8
d15
w(rst)
DD
= 2.5 V
A detailed description of the I
manual” . This may be found at www.nxp.com/acrobat_download/usermanuals/UM10204_3.pdf.
Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if SDA is held LOW for a
minimum of 25 ms.
Only applicable to the SC16IS750 and SC16IS760.
2 XTAL1 clocks or 3 s, whichever is less.
I
2
C-bus timing specifications
0.2 V, T
Parameter
SCL clock frequency
bus free time between a STOP and START
condition
hold time (repeated) START condition
set-up time for a repeated START
condition
set-up time for STOP condition
data hold time
data valid acknowledge time
data valid time
data set-up time
LOW period of the SCL clock
HIGH period of the SCL clock
fall time of both SDA and SCL signals
rise time of both SDA and SCL signals
pulse width of spikes that must be
suppressed by the input filter
I
I
I
I2C input pin interrupt valid time
I2C input pin interrupt clear time
I
I
I
SCL delay time after reset
reset pulse width
2
2
2
2
2
2
C-bus GPIO output valid time
C-bus modem input interrupt valid time
C-bus modem input interrupt clear time
C-bus receive interrupt valid time
C-bus receive interrupt clear time
C-bus transmit interrupt clear time
SS
amb
to V
= 40 C to +85 C; or V
DD
. All output load = 25 pF, except SDA output load = 400 pF.
2
C-bus specification, with applications, is given in user manual UM10204: “I
[1]
Single UART with I
DD
Rev. 06 — 13 May 2008
= 3.3 V
Conditions
SCL LOW to
data out valid
0.3 V, T
amb
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
= 40 C to +95 C; and refer to V
[2]
[3]
[4]
SC16IS740/750/760
Standard mode
Min
250
4.7
4.0
4.7
4.7
4.7
4.0
0.5
0.2
0.2
0.2
0.2
0.2
0.2
1.0
0
0
3
3
-
-
-
-
-
I
2
C-bus
1000
Max
100
300
0.6
0.6
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
C-bus specification and user
Min
150
1.3
0.6
0.6
0.6
1.3
0.6
0.5
0.2
0.2
0.2
0.2
0.2
0.2
0.5
Fast mode
0
0
3
3
-
-
-
-
-
© NXP B.V. 2008. All rights reserved.
I
2
C-bus
IL
Max
400
300
300
and V
0.6
0.6
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
IH
47 of 62
Unit
kHz
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
with