MAX3107EAG+ Maxim Integrated Products, MAX3107EAG+ Datasheet - Page 41

• Manufacturer Part Number: MAX3107EAG+
• Description: IC UART SPI/I2C 128 FIFO 24SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX3107EAG+

• Features: Internal Oscillators
• Number Of Channels: 4, QUART
• Fifo's: 128 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.35 V ~ 3.6 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Data Rate: 24 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.71 V
• Supply Current: 4 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PLLConfig—PLL Configuration Register
Table 4. PLLFactor[1:0] Selection Guide
Bits 7 and 6: PLLFactor[1:0]
The two PLLFactor[1:0] bits allow programming with select PLL’s multiplication factor. The input and output frequencies
of the PLL have to be limited to the ranges shown in Table 4. Enable the PLL through CLKSource[2].
Bits 5–0: PreDiv[5:0]
The six PreDiv[5:0] bits allow programming the divisor of the PLL’s predivider. The divisor must be chosen such that
the output frequency of the predivider, which equals the PLL’s input frequency, is limited to the ranges shown in Table 4.
The output frequency of the internal oscillator or the input frequency of XIN is f
PreDiv is an integer that must be in the range of 1 to 63.
Figure 14. PLL Signal Path
ADDRESS:
MODE:
RESET
PLLFactor1
NAME
BIT
0
0
1
1
PLLFactor1
______________________________________________________________________________________
7
0
PLLFactor0
0
1
0
1
0x1A
R/W
PLLFactor0
SPI/I
6
0
f
CLK
MULTIPLICATION
PREDIVIDER
FACTOR
PreDiv5
2
144
48
96
5
0
C UART with 128-Word FIFOs
6
f
PLLIN
PreDiv4
4
0
PLL
500kHz
850kHz
425kHz
390kHz
and Internal Oscillator
MIN
f
PreDiv3
REF
f
PLLIN
3
0
FRACTIONAL
GENERATOR
BAUD-RATE
800kHz
1.2MHz
667kHz
1MHz
MAX
CLK;
PreDiv2
2
0
f
PLLIN
40.8MHz
40.8MHz
56MHz
3MHz
MIN
= f
PreDiv1
CLK
1
0
/PreDiv (Figure 4).
f
REF
4.8MHz
56MHz
96MHz
96MHz
MAX
PreDiv0
0
1
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