MAX3107EAG+ Maxim Integrated Products, MAX3107EAG+ Datasheet - Page 35

• Manufacturer Part Number: MAX3107EAG+
• Description: IC UART SPI/I2C 128 FIFO 24SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX3107EAG+

• Features: Internal Oscillators
• Number Of Channels: 4, QUART
• Fifo's: 128 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.35 V ~ 3.6 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Data Rate: 24 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.71 V
• Supply Current: 4 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IrDA Register
The IrDA allows selection of IrDA SIR and MIR-compliant pulse shaping at the TX and RX interfaces. It also allows
inversion of the TX and RX logic, independently of whether IrDA is enabled or not.
Bits 7 and 6: No Function
Bit 5: TxInv
Set the TxInv bit high to invert the logic at the TX output. This is independent of IrDA operation.
Bit 4: RxInv
Set the RxInv bit high to invert the logic state at the RX input. This is independent of IrDA operation.
Bit 3: MIR
Set the MIR and IrDAEn bits high to select IrDA 1.1 (MIR) with 1/4 period pulse widths.
Bit 2: ShortIR
Set the ShortIR and IrDAEn bits high to select IrDA 1.0 (SIR) with the transmitter producing the minimum allowed pulse
widths of 1.63Fs.
Bit 1: SIR
Set the SIR bit and the IrDAEn bits high to select IrDA 1.0 pulses (SIR) with 3/16th period pulses.
Bit 0: IrDAEn
Set the IrDAEn bit high so that IrDA-compliant pulses are produced at the TX output and the MAX3107 receiver expects
such pulses at its Rx input. If IrDAEn is set to low (default), normal (nonIrDA) pulses are generated and expected at
the receiver. IrDAEn must be used in conjunction with the SIR, ShortIR, or MIR select bits.
FlowLvl—Flow Level Register
FlowLvl is used for selecting the RxFIFO threshold levels used for software (XON/XOFF) and hardware (RTS/CTS) flow control.
Bits 7–4: Resume[7:4]
Resume[7:4] sets the transmit FIFO threshold at which an XON is automatically sent or RTS/CLKOUT is automati-
cally set low. This signals the far-end station to start transmission. The actual threshold level is calculated as 8 times
Resume[7:4]. The resulting level is in the range of 0 to 120.
Bits 3–0: Halt[3:0]
Halt[3:0] sets a receive FIFO threshold level at which an XOFF is automatically sent or RTS/CLKOUT is automatically set
high, depending on whether auto software or hardware flow control is enabled. This signals the far-end station to halt
transmission. The actual threshold level is calculated as 8 times Halt[3:0]. Hence, the selectable threshold granularity
is eight. The resulting level is in the range of 0 to 120.
ADDRESS:
MODE:
ADDRESS:
MODE:
RESET
RESET
NAME
NAME
BIT
BIT
Resume3
______________________________________________________________________________________
—
7
0
7
0
0x0E
R/W
0x0F
R/W
Resume2
SPI/I
—
6
0
6
0
Resume1
2
TxInv
5
0
5
0
C UART with 128-Word FIFOs
Resume0
RxInv
4
0
4
0
and Internal Oscillator
Halt3
MIR
3
0
3
0
ShortIR
Halt2
2
0
2
0
Halt1
SIR
1
0
1
0
IrDAEn
Halt0
0
0
0
0
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