SC28L194A1BE,557 NXP Semiconductors, SC28L194A1BE,557 Datasheet - Page 38

• Manufacturer Part Number: SC28L194A1BE,557
• Description: IC UART QUAD W/FIFO 80-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC28L194A1BE,557

• Features: False-start Bit Detection
• Number Of Channels: 4, QUART
• Fifo's: 16 Byte
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1209; 935262730557; SC28L194A1BE

Philips Semiconductors
AC ELECTRICAL SPECIFICATIONS FOR COMMERCIAL AND INDUSTRIAL (3.3V)
V
2006 Aug 15
Reset Timing
Bus Timing
I/O Port Pin Timing
Interrupt Timing
Tx/Rx Clock Timing
Transmitter Timing
Receiver Timing
CC
SYMBOL
SYMBOL
Quad UART for 3.3 V and 5 V supply voltage
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
f
t
f
f
t
t
t
t
ts
RES
AS
AH
t
t
C
CH
STP
RWS
RWH
DD
DF
DS
DH
RWD
PS
PH
PD
PD
IR
IR
DD
RX
RX
TX
TX
TXD
TCS
RXS
RXH
CS
CS
STRT
= 3.3V
4
4
4
4
1
10%, –40 to +85 C
FIG #
FIG. #
RESET pulse width
A0–A7 setup time before Sclk C3 rising edge
A0–A7 hold time after Sclk C3 rising edge
CEN setup time before Sclk C1 high (Async)
CEN setup time before Sclk C2 high (Sync)
CEN hold time after Sclk C3 high (Sync)
CEN hold time after Sclk C4 high (Async)
CEN high before next C2 to stop next cycle (Sync Mode)
W–Rn setup time before Sclk C2 rising edge
W–Rn hold time after Sclk C3 rising edge
Read cycle Data valid after Sclk C3 falling edge
Read cycle data bus floating after CEN high (Async)
Read cycle data bus floating after C4 end (Sync)
Write cycle data setup time before Sclk C4 rising edge
Write cycle data hold time after Sclk C4 rising edge
High time between CEN low (Async)
I/O input setup time before Sclk C3 falling edge (Read IPR)
I/O input hold time after Sclk C4 rising edge
I/O output valid from:
IRQN from:
Interrupt vector valid after C3 rising edge
RxC high or low time
RxC frequency
RxC frequency
TxC high or low time
TxC frequency
TxC frequency
TxD output delay from TxC low
TxC output delay from TxD output data
RxD data setup time to RxC high (data)
RxD data hold time from RxC high (data)
RxD data low time for receiving a valid Start Bit
Write Sclk C4 rising edge (write to IOPIOR)
Internal interrupt source active bid
Reset to IRQN inactive
Write IMR (set or clear IMR bit)
(16 X)
(1 X)
(16 X)
(1 X)
PARAMETER
PARAMETER
3
38
2
17/32
MIN.
–15
10
22
30
25
50
30
25
25
25
15
18
12
22
25
20
25
25
8
8
7
0
0
0
0
1
1
1
LIMITS
1
1
1
1
/
TYP.
/
/
/
2
12
2
2
2
20
17
11
14
14
50
26
60
40
20
50
14
14
Sclk
3
3
3
4
4
8
7
4
Sclk
Sclk
Sclk
SC28L194
MAX.
Product data sheet
40
30
20
80
43
90
60
30
90
15
8
1
8
1
bit time
UNIT
UNIT
MHz
MHz
MHz
MHz
Sclk
Sclk
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns