SC16IS752IBS,151 NXP Semiconductors, SC16IS752IBS,151 Datasheet - Page 36

• Manufacturer Part Number: SC16IS752IBS,151
• Description: IC UART DUAL I2C/SPI 32-HVQFN
• Manufacturer: NXP Semiconductors
• Type: IrDA or RS- 232 or RS- 485r

Specifications of SC16IS752IBS,151

• Number Of Channels: 2, DUART
• Package / Case: 32-VFQFN Exposed Pad
• Features: Low Current
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 95 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-2236; 935279288151; SC16IS752IBS-S

NXP Semiconductors
SC16IS752_SC16IS762_7
Product data sheet
Fig 14. Data transfer on the I
Fig 15. Acknowledge on the I
SDA
SCL
condition
SCL from master
START
by transmitter
S
data output
data output
by receiver
MSB
A slave receiver must generate an acknowledge after the reception of each byte, and a
master must generate one after the reception of each byte clocked out of the slave
transmitter. When designing a system, it is necessary to take into account cases when
acknowledge is not received. This happens, for example, when the addressed device is
busy in a real-time operation. In such a case the master, after an appropriate ‘time-out’,
should abort the transfer by generating a STOP condition, allowing other transfers to take
place. These ‘other transfers’ could be initiated by other masters in a multimaster system,
or by this same master.
There are two exceptions to the ‘acknowledge after every byte’ rule. The first occurs when
a master is a receiver: it must signal an end of data to the transmitter by not signalling an
acknowledge on the last byte that has been clocked out of the slave. The acknowledge
related clock generated by the master should still take place, but the SDA line will not be
pulled down. In order to indicate that this is an active and intentional lack of
acknowledgement, we shall term this special condition as a ‘negative acknowledge’.
The second exception is that a slave will send a negative acknowledge when it can no
longer accept additional data bytes. This occurs after an attempted transfer that cannot be
accepted.
0
condition
START
S
1
2
2
C-bus
C-bus
interrupt within receiver
0
6
byte complete,
Dual UART with I
Rev. 07 — 19 May 2008
1
7
ACK
8
acknowledgement signal
from receiver
6
7
2
0
SC16IS752/SC16IS762
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
clock line held LOW
while interrupt is serviced
8
1
002aab013
2 to 7
transmitter stays off of the bus
during the acknowledge clock
acknowledgement signal
from receiver
ACK
8
© NXP B.V. 2008. All rights reserved.
condition
STOP
P
002aab012
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