SC16IS760IBS,151 NXP Semiconductors, SC16IS760IBS,151 Datasheet - Page 42

• Manufacturer Part Number: SC16IS760IBS,151
• Description: IC UART I2C/SPI 24-HVQFN
• Manufacturer: NXP Semiconductors
• Type: IrDA or RS- 232 or RS- 485r

Specifications of SC16IS760IBS,151

• Number Of Channels: 1, UART
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Features: Low Current
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-2238; 935279279151; SC16IS760IBS-S

NXP Semiconductors
SC16IS740_750_760_6
Product data sheet
Fig 22. Master writes to slave
Fig 23. Master read from slave
(1) See
(1) See
S
White block: host to SC16IS740/750/760
Grey block: SC16IS740/750/760 to host
White block: host to SC16IS740/750/760
Grey block: SC16IS740/750/760 to host
SLAVE ADDRESS
Table 33
Table 33
S
for additional information.
for additional information.
SLAVE ADDRESS
Table 33
SPI interfaces. Bit 0 is not used, bits 2:1 select the channel, bits 6:3 select one of the
UART internal registers. Bit 7 is not used with the I
SPI interface to indicate a read or a write operation.
The register read cycle (see
sending a slave address with the direction bit set to ‘write’ with a following subaddress.
Then, in order to reverse the direction of the transfer, the master issues a repeated START
followed again by the device address, but this time with the direction bit set to ‘read’. The
data bytes starting at the internal subaddress will be clocked out of the device, each
followed by a master-generated acknowledge. The last byte of the read cycle will be
followed by a negative acknowledge, signalling the end of transfer. The cycle is terminated
by a STOP signal.
Table 33.
Bit
7
6:3
2:1
0
W
and
Register address byte (I
Name
-
A[3:0]
CH1, CH0
-
Table 34
A
W
REGISTER ADDRESS
Single UART with I
show the bits’ presentation at the subaddress byte for I
A
Rev. 06 — 13 May 2008
REGISTER ADDRESS
Figure
Function
not used
UART’s internal register select
channel select: CH1 = 0, CH0 = 0
Other values are reserved and should not be used.
not used
2
(1)
C)
23) commences in a similar manner, with the master
A
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
nDATA
(1)
S
SC16IS740/750/760
A
2
C-bus interface, but it is used by the
SLAVE ADDRESS
A
nDATA
LAST DATA
A
002aab047
R
© NXP B.V. 2008. All rights reserved.
P
NA
A
2
002aab048
C-bus and
P
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