SI3220-KQ Silicon Laboratories Inc, SI3220-KQ Datasheet - Page 52

• Manufacturer Part Number: SI3220-KQ
• Description: IC SLIC/CODEC DUAL-CH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3220-KQ

• Package / Case: *
• Function: Subscriber Line Interface Concept (SLIC), CODEC
• Interface: GCI, PCM, SPI
• Number Of Circuits: 2
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 65mA
• Power (watts): 941mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Includes: Battery Switching, BORSCHT Functions, DTMF Generation and Decoding, FSK Tone Generation, Modem and Fax Tone Detection
• Product: Telecom
• Supply Voltage (min): 3.13 V
• Supply Current: 22 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Si3220/Si3225
Two-Wire Impedance Synthesis
Two-wire impedance synthesis is performed on-chip to
optimally match the output impedance of the Dual
ProSLIC to the impedance of the subscriber loop to
minimize the receive path signal reflected back onto the
transmit path. The Dual ProSLIC chipset provides on-
chip digitally programmable, two-wire
synthesis to meet return loss requirements against
virtually any global two-wire impedance requirement.
Real and complex two-wire impedances are realized by
a programmable digital filter block. (See Z block in
Figure 11 on page 22.)
52
Figure 33. Two-Wire Impedance Synthesis
V
TIP/RING
50
40
30
20
10
0
R
Configuration
0
S
Set VOCZERO bit to 1
V
(V)
Figure 32. Wink Function with Programmable Ramp Rate
OC
= 48 V
10
C
R
P
P
20
2 V/1.25 ms slope
set by RAMP bit
30
impedance
Preliminary Rev. 0.91
40
Set VOCZERO bit to 0
The two-wire impedance is programmed by loading the
desired real or complex impedance value into the
Si322X Coefficient Generator software in the format R
+ R
calculates the appropriate hex coefficients and loads
them
(registers 33–52). The two-wire impedance can be set
to any real or complex value within the boundaries set in
Table 30. The actual impedance presented to the
subscriber loop varies with series impedance from
protection devices placed between the Dual ProSLIC
chipset outputs and the TIP/RING pair according to the
following equation:
Where:
50
P
Desired
Configuration
R
R
R
||C
S
S
S
into
P
only
+ C
+ R
Table 30. Two-Wire Impedance
, as shown in Figure 33. The software
60
P
P
Z
to the TIP/RING pair
Z
||C
T
T
Synthesis Limitations
the
is the termination impedance presented
P
=
70
2R
PROT
appropriate
Programmable Limits
80
R
+
R
S
(
S
/(R
R
100–1000 Ω
x C
S
S
+
Time (ms)
P
+ R
R
P
> 0.5 ms
control
||
P
C
) > 0.1
P
)
registers
S