3222/3223-DB1 Silicon Laboratories Inc, 3222/3223-DB1 Datasheet - Page 30

• Manufacturer Part Number: 3222/3223-DB1
• Description: EVAL BOARD FOR IA3222/3223
• Manufacturer: Silicon Laboratories Inc
• Series: EZ DAA™r

Specifications of 3222/3223-DB1

• Main Purpose: Telecom, Data Acquisition Arrangement (DAA)
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: IA3222, IA3223
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

IA3222/23
In countries that have strong ring signals, setting one of the upper two thresholds (22.5 or 30 V
ring detection of most dial pulses. The first pulse may still be detected because the initial dial pulse or off-hook
transient may present a large signal to the ring-detection circuit. Subsequent dial pulses will fall below the ring
threshold as the dc-averaging circuit centers the ac waveform. This problem can be seen with all conventional ring
detectors. This is why ring-detection algorithms always need to qualify at least two ring cycles by ensuring they fall
within the time limits that correspond to the ring frequency.
In some countries, such as the UK and Australia, low ring thresholds are desired. Rather than setting ring
threshold, period, and number of valid cycles for every country, it is simpler to divide the whole world into a few
separate ring qualification groups. Valid ring signals are between 15 and 68 Hz. Ring cadences are usually less
than 2 seconds on but may be on as little as 0.2 seconds for distinctive ringing. If a 1 ms period resolution is
available, and assuming a tolerance of ±10% ±1 ms, the valid period range is 12 to 74 ms. These period limits
screen out 10 pps but not 20 pps pulse dialers. An example of two ring qualifier groups would be:


Line reversal (LR), line in use (LIU), or line activity (LACT) may also be used for ring detection in limited
circumstances. Line reversal is probably safe in high-ringer-threshold countries and would reject 20 pps dial pulses
effectively. In low-ringer-threshold countries, it may not reliably detect weak ring signals since the ringer signal
typically rides on top of the dc line voltage. If the ringer ac peaks are less than the line voltage, line reversal will not
occur.
LACT and LIU will almost always be triggered on any ring signal, but qualifying the ring frequency is a problem
because both detectors may produce more than one pulse per ring period. Although LACT is a sensitive full-wave
ring detector, full-wave ring detectors are less accurate with period because ring signals can be asymmetric either
because of origination or because of loading. In addition, the LACT detector is not as precise as the ring detector.
Its threshold may vary from 10 to 20 V peak.
Another ring-detection scheme makes use of the snoop audio output available at the RxOut pin. If the –6 dB snoop
gain is set (SGAIN bit set to zero) and if the CExt1 corner is placed correctly, the ring signal will be available in the
snoop audio path with sufficient attenuation to avoid clipping. A CExt1 of 10 nF will work well for typical 20 Hz ring
signals. If the ring signal is expected to be around 50 Hz, CExt1 should be reduced to 4.7 nF. This will increase the
–3 dB high-pass corner of the snoop audio path to about 700 Hz, which is normally acceptable for Caller ID signals.
6.3. Line Reversal
On-hook line reversal (not to be confused with off-hook loop current reversal) occurs in some countries instead of
the first ring cadence before the Caller ID message. Line reversal may also be used for other signaling. Typically,
many DAAs with line-reversal detection capability can only detect the transient and not the actual line polarity,
making it difficult to differentiate a line reversal from an off-hook transient. The IA3223 has a true line-polarity
detector. Line polarity is directly sensed in the IA3222 Line-Side chip, and this information is sent across the
isolation barrier to the IA3223 System-Side chip. Line polarity reversal may take up to 50 ms. Through this
transition, all three detectors, Line In Use, Line Activity, and Ring, may be triggered. A line reversal can be qualified
by determining if the change in polarity is stable for 50 to 100 ms.
6.4. Line Activity
The LACT detector can be programmed to drive the LineStat interrupt pin. This avoids the need for continuous
polling of either the LP (line polarity) or RNG (ring detection) bit. LACT detects 10 to 20 V changes in either
direction, also triggering on any ring, line reversal, or hook status change. When a LineStat interrupt occurs, the
system polls the RNG, LP, and LIU bits and applies qualification algorithms for about 100 ms or until line activity
stops.
30
Set lowest ring threshold (15 V
a row (disqualify if any period falls outside this range). This works worldwide except for 20 pps pulse dialing.
For strong ringer countries (e.g., North America and Japan), use the same criteria, but set the ring threshold to
30 V
RMS
.
RMS
), qualify ring period 12 to 74 ms, require at least two to three valid periods in
Rev. 5.0
RMS
) will prevent