NUC130VE3CN Nuvoton Technology Corporation of America, NUC130VE3CN Datasheet - Page 402

• Manufacturer Part Number: NUC130VE3CN
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130VE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Status Interrupts
A Status Interrupt is generated by bits BOff and EWarn (Error Interrupt) or by RxOk , TxOk, and
LEC (Status Change Interrupt) assumed that the corresponding enable bits in the CAN Control
Register are set. A change of bit EPass or a write to RxOk , TxOk , or LEC will never generate a
Status Interrupt.
Reading the Status Register will clear the Status Interrupt value (8000h) in the Interrupt
Register, if it is pending.
Error Code
NuMicro™ NUC130/NUC140 Technical Reference Manual
0
1
2
3
4
5
6
7
No Error
Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received
message where this is not allowed.
Form Error: A fixed format part of a received frame has the wrong format.
AckError: The message this CAN Core transmitted was not acknowledged by another
node.
Bit1Error: During the transmission of a message (with the exception of the arbitration field), the
device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus value
was dominant.
Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or
overload flag), though the device wanted to send a dominant level (data or identifier bit logical
value ‘0’), but the monitored Bus value was recessive. During busoff recovery, this status is set
each time a sequence of 11 recessive bits has been monitored. This enables the CPU to
monitor the proceedings of the busoff recovery sequence (indicating the bus is not stuck at
dominant or continuously disturbed).
CRCError: The CRC check sum was incorrect in the message received, the CRC received for
an incoming message does not match with the calculated CRC for the received data.
Unused: When the LEC shows the value ‘7’, no CAN bus event was detected since the CPU
wrote this value to the LEC.
to check for updates. Table 5-17 describes the error codes.
Table 5-17 Error Codes
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Meanings
Publication Release Date: June 14, 2011
Revision V2.01