SI2110-D-FMR Silicon Laboratories Inc, SI2110-D-FMR Datasheet - Page 30

• Manufacturer Part Number: SI2110-D-FMR
• Manufacturer: Silicon Laboratories Inc

Specifications of SI2110-D-FMR

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Si2107/08/09/10
6.5.3. Reed-Solomon Error Monitor
The Reed-Solomon error monitor is capable of counting
bit, byte, and uncorrectable packet errors. The error
type to be counted is controlled by the Reed-Solomon
error type register, RSERT. The Reed-Solomon error
mode bit, RSERM, controls whether the count is to be
performed over a fixed length or infinite window. The
window size is defined by RSERW. The BER count is
stored in a 16-bit saturating register, RSERC. Setting
the RS BER measurement start bit, RSERS, clears the
RSERC register and initiates the measurement. When
operating in the finite window mode, the RSERS bit is
automatically cleared when the measurement is
complete. The RSERS bit must be cleared manually in
the infinite mode, to stop the count.
6.5.4. PRBS BER Tester
To facilitate in-system pseudo random bit sequence
(PRBS) BER testing, the device provides the ability to
synchronize and track test sequences contained in the
payload (i.e., not SYNC bytes) of the MPEG data
stream. The user can define the payload of each TS
packet to exclude a number of header bytes, as set by
PRBS_HEADER_SIZE.
A PRBS test pattern must be encoded, modulated, and
injected into the channel to be monitored. The device
supports a PRBS 2
following polynomial:
To enable PRBS testing, the Reed-Solomon error type
register, RSERT, must be appropriately programmed.
After the device has synchronized to the incoming
PRBS test pattern, as indicated by PRBS_SYNC, errors
will be reported in the RSERC register.
Measurements can be performed at the output of the
Viterbi or Reed-Solomon decoder. To record errors at
the output of the Viterbi decoder, the Reed-Solomon
decoder and interleaver must be bypassed by setting
RS_BP and DI_BP in the “System Configuration”
section of the register map. To record errors at the
output of the Reed-Solomon block, the RS_BP bit must
be cleared.
30
G x ( )
23
– 1 bits long described by the
=
x
23
+
x
18
+
1
Rev. 1.0
6.5.5. Frame Synchronizer
The output of the Viterbi decoder is aligned into bytes by
detecting sync patterns within the data stream. In DVB-
S systems, the sync byte, 47h, occurs during the first
byte of a 204 byte RS code block. In DSS systems, a
sync byte, 1Dh, is appended to the beginning of each
RS encoded 146-byte block, resulting in 147-byte RS
code blocks. In DSS mode, sync bytes are discarded
before the byte stream is output to subsequent
decoding stages. When lock is achieved, the frame
synchronization lock bit, FSL, is asserted. If lock is not
achieved, the frame synchronizer fail bit, FSF, is
asserted.
The frame synchronizer commences under the control
of the acquisition sequencer.
Following frame synchronization lock, the device
examines the byte stream for a possible 180-degree
phase shift. If an inversion is detected, data are inverted
prior to being output.
6.6. Automatic Gain Control
The Si2107/08/09/10 is equipped with the ability to
adjust signal levels via an automatic gain control (AGC)
loop. This ensures that the noise and linearity
characteristics of the signal path are optimized at all
times. The AGC loop automatically adjusts the gain in
the analog signal chain and 2 points in the digital signal
chain.
6.6.1. Analog AGC
System gain is distributed into four independent stages
as shown in Figure 16. The gain range of all stages
combined is over 80 dB. When the AGC search
completes, the AGCL bit is asserted. If an error is
encountered during the AGC search, the AGCF bit is
also set. The AGC search commences under the
control of the acquisition sequencer.
The AGC loop works to automatically adjust the gain of
each stage to minimize the error between a measured
signal power and a desired output level. Signal power is
measured at the output of the ADC using an internal
rms power calculator. The result is stored in a 7-bit
saturating register, AGCPWR. The desired output level
is stored in the AGC threshold register, AGCTH. Signal
power measurements occur at a frequency dictated by
the AGC measurement window size, AGCW. This
frequency can be described using the following
equation, where fs equals the ADC sampling rate,
ADCSR.
AGC measurement frequency
=
------------------ - Hz
AGCW
f
s