SI2110-D-FMR Silicon Laboratories Inc, SI2110-D-FMR Datasheet - Page 27

• Manufacturer Part Number: SI2110-D-FMR
• Manufacturer: Silicon Laboratories Inc

Specifications of SI2110-D-FMR

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Supplier Unconfirmed

6.3. Receiver Status
During receive operation, the host can retrieve
information on the status of AGC lock (AGCL), carrier
estimation lock (CEL), symbol rate estimation lock
(SRL), symbol timing lock (STL), carrier recovery lock
(CRL), Viterbi decoder lock (VTL), frame sync lock
(FSL), and overall receiver lock (RCVL).
During channel acquisition, the host can retrieve
information on error conditions due to AGC search
(AGCF), carrier estimation (CEF), symbol rate search
(SRF), symbol timing search (STF), carrier recovery
search (CRF), Viterbi code rate search (VTF), frame
sync search (FSF), and overall receiver acquisition
(AQF),
6.4. Tuning Control
The Si2107/08/09/10 utilizes a unique two-stage tuning
algorithm to provide optimal RF reception. The input
signal is first mixed down to a low-IF frequency by a
coarse tuning stage and then down to baseband by a
fine-tune mixer. The user programs both coarse and
fine-tuning frequencies using the CTF and FTF
registers.
An algorithm (supplied with the reference software
driver) is used to automatically calculate the required
values. As part of the tuning process, the sample rate,
fs, should also be programmed via the ADCSR register.
Values between 192 and 207 MHz are supported. An
algorithm is supplied with the reference software driver
to automatically select the optimal sampling rate.
6.4.1. Automatic Acquisition
The receiver acquisition sequence consists of the
following stages: Analog AGC Search, Carrier Offset
Estimation, Symbol Rate Estimation, Symbol Timing
Recovery, Carrier Recovery, Viterbi Search, and Frame
Synchronization. For the receiver to lock, each stage
must run to completion or declare lock as shown in
Figure 14. If a given stage is unable to achieve lock
after
exceeding the timeout period, it asserts a fail signal.
To initiate the acquisition sequence, the user should
program the acquisition start bit, AQS. All search
parameters must be specified before initiating the
acquisition.
sequence, the AQS bit is automatically cleared. The
acquisition sequence can be aborted at any time by
clearing the AQS bit.
The status of the acquisition sequence can be
monitored via the registers in the receiver status register
map section. A successful acquisition is reported by the
assertion of the receiver lock bit, RCVL. A failed
acquisition is reported by the assertion of the acquisition
exhausting
Upon
a
completion
parameter
of
search
the
acquisition
range
Rev. 1.0
or
fail bit, AQF.
6.4.2. Carrier Offset Estimation
The desired carrier frequency may be offset from its
nominal position due to the imperfections and
temperature dependencies of the LNB. The carrier
offset estimator uses a search procedure to identify,
track, and remove this frequency offset from the system.
Carrier offset estimation supports two modes: legacy
mode and QuickLock. QuickLock features decreased
search times and enhanced search ranges. Silicon
Laboratories highly recommends the use of Quicklock
mode. Legacy mode is supported for backwards
compatibility with revision C of Si2107/08.
The mode selection is programmed with the COEMS
bit.
Stage fail
Stage fail
Stage fail
Stage fail
Stage fail
Stage fail
unlocked
and STL
Figure 14. Acquisition Sequence (Symbol Rate
1. Acquisition fail if stage fails n times in a row .
2. Acquisition fail if stage completes parameter range
Estimation Available on Si2109/10 Only)
without locking.
Symbol Rate Estimation
Carrier Frequency Loop
Symbol Timing Loop
Analog AGC Search
Acquisition Start
CFO Estimation
Receiver locked
Si2107/08/09/10
Viterbi Search
Frame Search
Calibration
LO Tuning
done
done
done
lock
lock
lock
2
2
1
1
1
1
STL is locked
Stage fail but
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