SI2110-D-FM Silicon Laboratories Inc, SI2110-D-FM Datasheet - Page 25

• Manufacturer Part Number: SI2110-D-FM
• Manufacturer: Silicon Laboratories Inc

Specifications of SI2110-D-FM

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

6.2. Interrupts
The device is equipped with several sticky interrupt bits
to provide precise event tracking and monitoring.
Next to interrupts being signaled via the I
map, the user can program one of the device terminals
(INT) as a dedicated interrupt pin via the pin select
register bit, PSEL. The device contains an extensive
collection of interrupt sources that can be individually
masked from the INT pin using the corresponding
interrupt enable register bits, labeled with suffix “_E”.
Thus, the INT output is a logical-OR of all enabled
interrupts. Generation of the channel interrupt on pin
Receiver lock
Receiver unlock
AGC lock
AGC failure
AGC threshold
Carrier estimation failure
Symbol rate est. lock
Symbol rate est. failure
Symbol timing lock
Symbol timing unlock
Carrier recovery lock
Carrier recovery unlock
Viterbi lock
Viterbi unlock
Frame synchronizer lock
Frame synchronizer unlock
Acquisition fail
C/N measurement complete
Viterbi BER measurement complete
RS measurement complete
Message FIFO empty
Message FIFO full
Message received
Message parity error
Message receive timeout
Short-circuit detect
Over current detect
Carrier estimation lock
Event
Table 16. Events, Interrupts, and Status Bits
2
C register
Interrupt Bit
MSGTO_I
MSGPE_I
AGCTS_I
MSGR_I
RCVU_I
RSER_I
RCVL_I
AGCL_I
VTER_I
CRU_I
SCD_I
OCD_I
STU_I
CRL_I
VTU_I
FSU_I
AQF_I
CEL_I
STL_I
VTL_I
FSL_I
CN_I
FE_I
FF_I
Rev. 1.0
INT can be masked off by using the interrupt enable bit,
INT_EN. Note that interrupt reporting in the register
map is not affected by INT_EN.
The interrupt signal polarity can be configured to be
active high or active low using the interrupt polarity bit,
INTP. The interrupt signal type can be configured to be
CMOS output or open-drain/source output using the
interrupt type bit, INTT. Interrupt bits are set by the
device to 1 when an interrupt occurs. The host clears an
interrupt bit by writing a 1 again, at which time the
device resets the interrupt bit to zero. Table 16
illustrates the interrupt sources and their associated
status, enable, and interrupt bits.
Enable Bit
MSGTO_E
MSGPE_E
AGCTS_E
MSGR_E
RCVU_E
RSER_E
RCVL_E
AGCL_E
VTER_E
CRU_E
OCD_E
STU_E
CRL_E
FSU_E
AQF_E
SCD_E
CEL_E
VTU_E
STL_E
VTL_E
FSL_E
CN_E
FE_E
FF_E
Si2107/08/09/10
AGCTS (0 –> 1)
AGCL (0 –> 1)
RCVL (1 –> 0)
RCVL (0 –>1)
AGCF (0->1)
CRL (0 –> 1)
CRL (1 –> 0)
AQF (0 –> 1)
CEL (0 –> 1)
SRL (0 –> 1)
STL (0 –> 1)
STL (1 –> 0)
VTL (0 –> 1)
VTL (1 –> 0)
FSL (0 –> 1)
FSL (1 –> 0)
SRF (0->1)
Status Bit
CEF(0->1)
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