M24C16-MN6T STMicroelectronics, M24C16-MN6T Datasheet - Page 4

• Manufacturer Part Number: M24C16-MN6T
• Description: EEPROM Serial-I2C 16K-Bit 2K x 8 5V 8-Pin SO N T/R
• Manufacturer: STMicroelectronics

Specifications of M24C16-MN6T

• Package: 8SO N
• Interface Type: Serial-I2C
• Density: 16 Kb
• Maximum Operating Frequency: 0.4 MHz
• Maximum Random Access Time: 900 ns
• Typical Operating Supply Voltage: 5 V
• Organization: 2Kx8
• Data Retention: 40(Min) Year
• Hardware Data Protection: Yes
• Operating Temperature: -40 to 85 °C

M24C16, M24C08, M24C04, M24C02, M24C01
SUMMARY DESCRIPTION
These I
grammable memory (EEPROM) devices are orga-
nized as 2048/1024/512/256/128 x 8 (M24C16,
M24C08, M24C04, M24C02, M24C01).
Figure 2. Logic Diagram
I
bi-directional data line and a clock line. The devic-
es carry a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I
The device behaves as a slave in the I
with all memory operations synchronized by the
serial clock. Read and Write operations are initiat-
ed by a Start condition, generated by the bus mas-
ter. The Start condition is followed by a Device
Select Code and RW bit (as described in
terminated by an acknowledge bit.
Figure 3. DIP, SO, TSSOP and MLP Connections (Top View)
Note: 1. NC = Not Connected
4/29
2
C uses a two wire serial interface, comprising a
2. See
E0-E2
SCL
WC
2
C-compatible electrically erasable pro-
PACKAGE MECHANICAL
3
V CC
V SS
M24Cxx
16Kb
NC
NC
NC
/8Kb
/ E2
/ NC
/ NC
2
/4Kb
/ E1
/ E2
section for package dimensions, and how to identify pin-1.
/ NC
C bus definition.
/2Kb
/ E0
/ E1
/ E2
AI02033
2
SDA
C protocol,
/1Kb
/ E0
/ E1
/ E2
V SS
Table
1
2
3
4
2.),
M24Cxx
8
7
6
5
When writing data to the memory, the device in-
serts an acknowledge bit during the 9
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Table 1. Signal Names
Power On Reset: V
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. At Power-up, the
internal reset is held active until V
the POR threshold value, and all operations are
disabled – the device will not respond to any com-
mand. In the same way, when V
operating voltage, below the POR threshold value,
all operations are disabled and the device will not
respond to any command.
A stable and valid V
Table
ic signal.
V CC
WC
SCL
SDA
E0, E1, E2
SDA
SCL
WC
V
V
CC
SS
7.) must be applied before applying any log-
CC
CC
Chip Enable
Serial Data
Serial Clock
Write Control
Supply Voltage
Ground
(as defined in
AI02034E
Lock-Out Write Protect
CC
CC
drops from the
has reached
Table 6.
th
bit time,
and