CY7C131-15JI Cypress Semiconductor Corp, CY7C131-15JI Datasheet - Page 9

• Manufacturer Part Number: CY7C131-15JI
• Description: SRAM Chip Async Dual 5V 8K-Bit 1K x 8 15ns 52-Pin PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C131-15JI

• Package: 52PLCC
• Timing Type: Asynchronous
• Density: 8 Kb
• Typical Operating Supply Voltage: 5 V
• Address Bus Width: 10 Bit
• Number Of I/o Lines: 8 Bit
• Number Of Ports: 2
• Number Of Words: 1K

Switching Waveforms
Document #: 38-06002 Rev. *D
Write Cycle No. 1 (OE Three-States Data I/Os—Either Port
Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)
Notes:
ADDRESS
22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
23. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
ADDRESS
DATA
DATA
D
and for data to be placed on the bus for the required t
DATA
OUT
R/W
OE
CE
R/W
OUT
IN
CE
IN
t
HZOE
(continued)
t
SA
t
SA
SD
.
t
SCE
t
SCE
t
AW
t
AW
t
Either Port
HZWE
t
WC
t
WC
[15, 22]
[16, 23]
HIGH IMPEDANCE
t
PWE
DATA VALID
t
PWE
t
SD
PWE
HIGH IMPEDANCE
or t
t
DATA VALID
SD
HZWE
+ t
SD
t
to allow the data I/O pins to enter high impedance
HD
t
HD
t
LZWE
t
HA
t
HA
CY7C130/CY7C131
CY7C140/CY7C141
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