CY7C025-25JI Cypress Semiconductor Corp, CY7C025-25JI Datasheet - Page 15

• Manufacturer Part Number: CY7C025-25JI
• Description: SRAM Chip Async Dual 5V 128K-Bit 8K x 16 25ns 84-Pin PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C025-25JI

• Package: 84PLCC
• Timing Type: Asynchronous
• Density: 128 Kb
• Typical Operating Supply Voltage: 5 V
• Address Bus Width: 12 Bit
• Number Of I/o Lines: 16 Bit
• Number Of Ports: 2
• Number Of Words: 8K

Architecture
The CY7C024/0241 and CY7C025/0251 consist of an array of
4K words of 16/18 bits each and 8K words of 16/18 bits each
of dual-port RAM cells, I/O and address lines, and control sig-
nals (CE, OE, R/W). These control pins permit independent access
for reads or writes to any location in memory. To handle simultaneous
writes/reads to the same location, a BUSY pin is provided on each
port. Two interrupt (INT) pins can be utilized for port-to-port commu-
nication. Two semaphore (SEM) control pins are used for allocating
shared resources. With the M/S pin, the CY7C024/0241 and
CY7C025/0251 can function as a master (BUSY pins are outputs) or
as a slave (BUSY pins are inputs). The CY7C024/0241 and
CY7C025/0251 have an automatic power-down feature controlled by
CE. Each port is provided with its own output enable control (OE),
which allows data to be read from the device.
Functional Description
Write Operation
Data must be set up for a duration of t
of R/W in order to guarantee a valid write. A write operation is con-
trolled by either the R/W pin (see Write Cycle No. 1 waveform) or the
CE pin (see Write Cycle No. 2 waveform). Required inputs for
non-contention operations are summarized in Table 1 .
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output; other-
wise the data read is not deterministic. Data will be valid on the
port t
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available t
asserted. If the user of the CY7C024/0241 or CY7C025/0251 wishes
to access a semaphore flag, then the SEM pin must be asserted
instead of the CE pin, and OE must also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (FFF for the
CY7C024/0241, 1FFF for the CY7C025/0251) is the mailbox
for the right port and the second-highest memory location
(FFE for the CY7C024/0241, 1FFE for the CY7C025/0251) is
the mailbox for the left port. When one port writes to the other
port’s mailbox, an interrupt is generated to the owner. The in-
terrupt is reset when the owner reads the contents of the mail-
box. The message is user defined.
Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the BUSY signal (to a port)
prevents the port from setting the interrupt to the winning port.
Also, an active BUSY to a port prevents that port from reading
its own mailbox and thus resetting the interrupt to it.
If your application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy
are summarized in Table 2.
Busy
The CY7C024/0241 and CY7C025/0251 provide on-chip arbi-
tration to resolve simultaneous memory location access (con-
DDD
after the data is presented on the other port.
ACE
after CE or t
SD
before the rising edge
DOE
after OE is
15
tention). If both ports’ CEs are asserted and an address match
occurs within t
port has access. If t
sion to the location, but which one is not predictable. BUSY will be
asserted t
Master/Slave
A M/S pin is provided in order to expand the word width by configuring
the device as either a master or a slave. The BUSY output of the
master is connected to the BUSY input of the slave. This will allow the
device to interface to a master device with no external components.
Writing to slave devices must be delayed until after the BUSY input
has settled (t
cycle during a contention situation.When tied HIGH, the M/S pin al-
lows the device to be used as a master and, therefore, the BUSY line
is an output. BUSY can then be used to send the arbitration outcome
to a slave.
Semaphore Operation
The CY7C024/0241 and CY7C025/0251 provide eight sema-
phore latches, which are separate from the dual-port memory
locations. Semaphores are used to reserve resources that are
shared between the two ports.The state of the semaphore in-
dicates that a resource is in use. For example, if the left port
wants to request a given resource, it sets a latch by writing a
zero to a semaphore location. The left port then verifies its
success in setting the latch by reading it. After writing to the
semaphore, SEM or OE must be deasserted for t
tempting to read the semaphore. The semaphore value will be avail-
able t
left port was successful (reads a zero), it assumes control of the
shared resource, otherwise (reads a one) it assumes the right port
has control and continues to poll the semaphore. When the right side
has relinquished control of the semaphore (by writing a one), the left
side will succeed in gaining control of the semaphore. If the left side
no longer requires the semaphore, a one is written to cancel its re-
quest.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE must
remain HIGH during SEM LOW). A
address. OE and R/W are used in the same manner as a normal
memory access. When writing or reading a semaphore, the other
address pins have no effect.
When writing to the semaphore, only I/O
written to the left port of an available semaphore, a one will appear at
the same semaphore address on the right port. That semaphore can
now only be modified by the side showing zero (the left port in this
case). If the left port now relinquishes control by writing a one to the
semaphore, the semaphore will be set to one for both sides. However,
if the right port had requested the semaphore (written a zero) while
the left port had control, the right port would immediately own the
semaphore as soon as the left port released it. Table 3 shows sample
semaphore operations.
When reading a semaphore, all sixteen/eighteen data lines
output the semaphore value. The read value is latched in an
output register to prevent the semaphore from changing state
during a write from the other port. If both ports attempt to ac-
cess the semaphore within t
definitely be obtained by one side or the other, but there is no guaran-
tee which side will control the semaphore.
SWRD
BLA
+ t
BLC
after an address match or t
DOE
PS
or t
of each other, the busy logic will determine which
after the rising edge of the semaphore write. If the
PS
BLA
is violated, one port will definitely gain permis-
). Otherwise, the slave chip may begin a write
SPS
of each other, the semaphore will
0–2
CY7C024/0241
CY7C025/0251
represents the semaphore
BLC
after CE is taken LOW.
0
is used. If a zero is
SOP
before at-