CY7C025-25JI Cypress Semiconductor Corp, CY7C025-25JI Datasheet - Page 10

• Manufacturer Part Number: CY7C025-25JI
• Description: SRAM Chip Async Dual 5V 128K-Bit 8K x 16 25ns 84-Pin PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C025-25JI

• Package: 84PLCC
• Timing Type: Asynchronous
• Density: 128 Kb
• Typical Operating Supply Voltage: 5 V
• Address Bus Width: 12 Bit
• Number Of I/o Lines: 16 Bit
• Number Of Ports: 2
• Number Of Words: 8K

Switching Waveforms
Write Cycle No. 2: CE Controlled Timing
Write Cycle No. 1: R/W Controlled Timing
Notes:
23. R/W must be HIGH during all address transitions.
24. A write occurs during the overlap (t
25. t
26. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
27. To access RAM, CE = V
28. To access upper byte, CE = V
29. Transition is measured 500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
30. During this period, the I/O pins are in the output state, and input signals must not be applied.
31. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
CE
DATA OUT
ADDRESS
ADDRESS
CE
DATA IN
DATA IN
[27,28]
the bus for the required t
To access lower byte, CE = V
HA
[27,28]
R/W
R/W
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
OE
SD
IL
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
, SEM = V
IL
, LB = V
IL
(continued)
t
t
, UB = V
SA
SA
NOTE 30
IH
SCE
IL
.
, SEM = V
IL
or t
, SEM = V
PWE
) of a LOW CE or SEM and a LOW UB or LB.
IH
.
t
[23, 24, 25, 31]
IH
HZWE
.
[23, 24, 25, 26]
[29]
t
t
AW
AW
t
t
WC
WC
t
t
SCE
PWE
[26]
10
t
t
PWE
SD
SD
or (t
HZWE
+ t
SD
t
t
HA
HA
) to allow the I/O drivers to turn off and data to be placed on
t
t
HD
HD
t
LZWE
CY7C024/0241
CY7C025/0251
t
HZOE
NOTE 30
[29]
7C024–17
7C024–18
PWE
.