AM29F010A-45JC AMD (ADVANCED MICRO DEVICES), AM29F010A-45JC Datasheet - Page 2

• Manufacturer Part Number: AM29F010A-45JC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM29F010A-45JC

• Lead Free Status / Rohs Status: Not Compliant

GENERAL DESCRIPTION
The Am29F010A is a 1 Mbit, 5.0 Volt-only Flash
memory organized as 131,072 bytes. The Am29F010A
is offered in 32-pin PLCC and TSOP packages. The
byte-wide data appears on DQ0-DQ7. The device is
designed to be programmed in-system with the standard
system 5.0 Volt V
for program or erase operations. The device can also be
programmed or erased in standard EPROM programmers.
This device is manufactured using AMD’s 0.55 µm pro-
cess technology, and offers all the features and benefits
of the Am29F010, which was manufactured using 0.85
µm process technology. In addition, the Am29F010A
offers the erase suspend/erase resume feature.
The standard device offers access times of 45, 55, 70,
90, and 120 ns, allowing high-speed microprocessors
to operate without wait states. To eliminate bus conten-
tion the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a single 5.0 volt power sup-
ply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This invokes the Embedded
Program algorithm—an internal algorithm that auto-
2
CC
supply. A 12.0 volt V
PP
is not required
Am29F010A
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This invokes the Embedded Erase
algorithm—an internal algorithm that automatically pre-
programs the array (if it is not already programmed)
before executing the erase operation. During erase,
the device automatically times the erase pulse widths
and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the device is ready
to read array data or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is erased
when shipped from the factory.
The hardware data protection measures include a
low V
during power transitions. The hardware sector protec-
tion feature disables both program and erase
operations in any combination of the sectors of memory,
a n d i s i m p l e m e n t e d u s i n g s t a n d a r d E P R O M
programmers.
The system can place the device into the standby mode.
Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
h i g h e s t l eve l s o f q u a l i t y, r e l i a b i l i t y, a n d c o s t
effectiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte at a
time using the EPROM programming mechanism of
hot electron injection.
CC
detector automatically inhibits write operations