TE28F160S570 Intel, TE28F160S570 Datasheet - Page 6

• Manufacturer Part Number: TE28F160S570
• Manufacturer: Intel

Specifications of TE28F160S570

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 4.5 to 5.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

28F160S5/28F320S5
Individual block locking uses a combination of block
lock-bits to lock and unlock blocks. Block lock-bits
gate block erase, full chip erase, program and write
to
operations (Set Block Lock-Bit and Clear Block
Lock-Bits commands) set and clear lock-bits.
The status register and the STS pin in RY/BY#
mode indicate whether or not the device is busy
executing an operation or ready for a new
command. Polling the status register, system
software retrieves WSM feedback. STS in RY/BY#
mode gives an additional indicator of WSM activity
by providing a hardware status signal. Like the
status register, RY/BY#-low indicates that the WSM
is performing a block erase, program, or lock-bit
operation. RY/BY#-high indicates that the WSM is
ready for a new command, block erase is
suspended (and program is inactive), program is
suspended, or the device is in deep power-down
mode.
The Automatic Power Savings (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
6
16-Mbit: A
32-Mbit: A
buffer
0
0 -
- A
A
20
21
operations.
Input Buffer
Address
Address
Counter
Latch
Lock-bit
Figure 1. 28F320S5 and 28F160S5 Block Diagram
Y-Decoder
X-Decoder
configuration
Output Buffer
Comparator
16-Mbit: Thirty-two
32-Mbit: Sixty-four
Identifier
DQ
Register
Register
64-Kbyte Blocks
Status
Query
Data
0
Y-Gating
- DQ
The BYTE# pin allows either x8 or x16 read/writes
to the device. BYTE# at logic low selects 8-bit
mode with address A
byte and high byte. BYTE# at logic high enables
16-bit operation with address A
lowest order address. Address A
16-bit mode.
When one of the CE
pins are at V
standby mode. Driving RP# to GND enables a deep
power-down mode which significantly reduces
power consumption, provides write protection,
resets the device, and clears the status register. A
reset time (t
high until outputs are valid. Likewise, the device
has a wake time (t
to the CUI are recognized.
1.3
The 16-Mbit device is available in the 56-lead
TSOP and 56-lead SSOP. The 32-Mb device is
available in the 56-lead SSOP. The pinouts are
shown in Figures 2 and 3.
15
Input Buffer
Multiplexer
Pinout and Pin Description
PHQV
CC
, the component enters a CMOS
) is required from RP# switching
PHEL
X
Write State
# pins (CE
Machine
0
Command
Interface
) from RP#-high until writes
User
selecting between the low
PRELIMINARY
0
Program/Erase
#, CE
Voltage Switch
1
0
I/O Logic
is not used in
becoming the
1
#) and RP#
STS
WE#
WP#
CE#
OE#
RP#
V
BYTE#
V
V
GND
0609_01
CC
PP
CC