TE28F160S570 Intel, TE28F160S570 Datasheet - Page 12

• Manufacturer Part Number: TE28F160S570
• Manufacturer: Intel

Specifications of TE28F160S570

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 4.5 to 5.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

28F160S5/28F320S5
12
Figure 5. Device Identifier Code Memory Map
Address
Word
0FFFF
07FFF
08004
08003
08002
08000
00004
00003
00002
00001
00000
Block 1 Lock Configuration
Block 0 Lock Configuration
(Subsequent Blocks)
Reserved for Future
Reserved for Future
Reserved for Future
Manufacturer Code
A[
A[
Implementation
Implementation
Implementation
Device Code
20-1
21-1
]: 16-Mbit
]: 32-Mbit
Block 1
Block 0
0609_05
3.7
Writing commands to the CUI enables reading of
device data, query, identifier codes, inspection
and clearing of the status register. Additionally,
when V
and lock-bit configuration can also be performed.
The Block Erase command requires appropriate
command data and an address within the block
to be erased. The Byte/Word Write command
requires the command and address of the
location to be written. Set Block Lock-Bit
commands require the command and address
within the block to be locked. The Clear Block
Lock-Bits command requires the command and
an address within the device.
The CUI does not occupy an addressable
memory location. It is written when WE#, CE
and CE
and data needed to execute a command are
latched on the rising edge of WE# or CE
(CE
Standard microprocessor write timings are used.
Figure 17 illustrates a write operation.
4.0
V
from the status register, identifier codes, or
memory blocks. Placing V
successful block erase, programming, and lock-
bit configuration operations.
Device operations are selected by writing specific
commands into the CUI. Table 2 and Table 3
define these commands.
PP
0
#,
voltage
1
PP
COMMAND DEFINITIONS
# are active and OE# = V
CE
Write
= V
1
#),
PPH
V
PPLK
, block erasure, programming,
whichever
PRELIMINARY
enables read operations
PPH
goes
on V
IH
. The address
PP
high
enables
first.
0
X
#,
#