MC68HC711KS2CFN3 Freescale Semiconductor, MC68HC711KS2CFN3 Datasheet - Page 211
MC68HC711KS2CFN3
Manufacturer Part Number
MC68HC711KS2CFN3
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68HC711KS2CFN3.pdf
(290 pages)
Specifications of MC68HC711KS2CFN3
Cpu Family
HC11
Device Core Size
8b
Frequency (max)
4MHz
Interface Type
SCI/SPI
Program Memory Type
ROM
Program Memory Size
32KB
Total Internal Ram Size
1KB
# I/os (max)
51
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
On-chip Adc
8-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
68
Package Type
PLCC
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC711KS2CFN3
Manufacturer:
NSC
Quantity:
1 001
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9.9 Pulse-Width Modulator (PWM)
9.9.1 PWM System Description
M68HC11K Family
MOTOROLA
Four 8-bit pulse-width modulation channels are available in the
M68HC11K Family devices. They are output on port H pins 3–0. Pairs of
channels can be concatenated to produce 16-bit outputs. Three
programmable clocks and a flexible clock selection scheme provide a
wide range of frequencies.
The 8-bit mode with E = 4 MHz can produce waveforms from 40 kHz at
1 percent duty cycle resolution to less than 10 Hz at 0.4 percent duty
cycle resolution. In 16-bit mode, a duty cycle resolution down to 15 parts
per million can be achieved (at a frequency of 60 Hz). At 1 kHz, the duty
cycle resolution is 250 ppm.
Figure 9-30
channels is enabled by bit PWENx in the PWEN register. Each channel
has an 8-bit counter (PWCNTx), a period register (PWPERx), and a duty
cycle register (PWDTYx). The counter is driven by one of three
user-scaled clock sources — clock A, B, or S — selected by the
pulse-width channel select (PCLKx) bit in the pulse-width modulation
timer polarity (PWPOL) register.
A pulse-width modulation period begins when the counter matches the
value stored in the period register. When this happens, a logic value
determined by the polarity bit (PPOLx) in the PWPOL register is driven
on the associated port H output pin, and the counter is reset to 0. When
the counter matches the number stored in the duty cycle register, the
output reverses polarity. The period and duty cycle registers are double
buffered so they can be changed without disturbing the current
waveform. A new period or duty cycle can be forced by writing to the
period (PWPERx) or duty cycle register (PWDTYx) and then to the
counter (PWCNTx). Writing to the counter always resets it to 0.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
shows a block diagram of the PWM system. Each of four
Timing System
Pulse-Width Modulator (PWM)
Timing System
Technical Data
211
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