MC68HC711KS2CFN3 Freescale Semiconductor, MC68HC711KS2CFN3 Datasheet - Page 110

• Manufacturer Part Number: MC68HC711KS2CFN3
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC711KS2CFN3

• Cpu Family: HC11
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI/SPI
• Program Memory Type: ROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Resets and Interrupts
5.3.3.3 Arm/Reset COP Timer Circuitry Register
5.3.4 Clock Monitor Reset
Technical Data
110
NOTE:
Address: $003A
To prevent a COP reset, this sequence must be completed:
Performing instructions between these two steps is possible as long as
both steps are completed in the correct sequence before the timer times
out.
The clock monitor can serve as a backup for the COP system. Its circuit
is based on an internal RC time delay. If no MCU clock edges are
detected within this RC time delay, the clock monitor generates a system
reset. Because the COP needs a clock to function, it is disabled when
the clocks stop. Thus, the clock monitor system can detect clock failures
not detected by the COP system.
Reset:
Figure 5-3. Arm/Reset COP Timer Circuitry Register (COPRST)
Read:
Write:
1. Write $55 to COPRST to arm the COP timer clearing mechanism.
2. Write $AA to COPRST to clear the COP timer.
Freescale Semiconductor, Inc.
For More Information On This Product,
Bit 7
Bit 7
0
Go to: www.freescale.com
Resets and Interrupts
Bit 6
6
0
Bit 5
5
0
Bit 4
4
0
Bit 3
3
0
Bit 2
2
0
M68HC11K Family
Bit 1
1
0
MOTOROLA
Bit 0
Bit 0
0