A40MX04-FPQG100 MICROSEMI, A40MX04-FPQG100 Datasheet - Page 48

• Manufacturer Part Number: A40MX04-FPQG100
• Manufacturer: MICROSEMI

Specifications of A40MX04-FPQG100

• Family Name: 40MX
• Number Of Usable Gates: 6000
• Number Of Logic Blocks/elements: 547
• # Registers: 273
• # I/os (max): 69
• Frequency (max): 50/83MHz
• Process Technology: 0.45um (CMOS)
• Operating Supply Voltage (typ): 3.3/5V
• Logic Cells: 547
• Device System Gates: 6000
• Propagation Delay Time: 3.7/2.7ns
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / Rohs Status: Compliant

Table 30 •
1 -4 2
Parameter Description
Logic Module Propagation Delays
t
t
t
t
t
Logic Module Predicted Routing Delays
t
t
t
t
t
Logic Module Sequential Timing
t
t
t
t
t
t
t
f
Input Module Propagation Delays
t
t
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to check the hold
4. Delays based on 35 pF loading.
PD1
PD2
CO
GO
RS
RD1
RD2
RD3
RD4
RD8
SUD
HD
SUENA
HENA
WCLKA
WASYN
A
MAX
INYH
INYL
40MX and 42MX FPGA Families
3
device performance. Post-route timing analysis or simulation is required to determine actual performance.
time for this macro.
A40MX04 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, V
Single Module
Dual-Module Macros
Sequential Clock-to-Q
Latch G-to-Q
Flip-Flop (Latch) Reset-to-Q
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Flip-Flop (Latch) Data Input Set-Up
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
Flip-Flop (Latch) Clock Active
Pulse Width
Flip-Flop (Latch)
Asynchronous Pulse Width
Flip-Flop Clock Input Period
Flip-Flop (Latch) Clock Frequency
(FO = 128)
Pad-to-Y HIGH
Pad-to-Y LOW
2
1
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
‘–3’ Speed
3.1
0.0
3.1
0.0
3.3
3.3
4.8
CC
181
1.2
2.3
1.2
1.2
1.2
1.2
1.9
2.4
2.9
5.0
0.7
0.6
= 4.75V, T
v6.1
‘–2’ Speed
3.5
0.0
3.5
0.0
3.8
3.8
5.6
J
= 70°C)
167
1.4
3.1
1.4
1.4
1.4
1.6
2.2
2.8
3.4
5.8
0.8
0.7
‘–1’ Speed
4.0
0.0
4.0
0.0
4.3
4.3
6.3
154
1.6
3.5
1.6
1.6
1.6
1.8
2.5
3.2
3.9
6.6
0.9
0.8
‘Std’ Speed
4.7
0.0
4.7
0.0
5.0
5.0
7.5
134
1.9
4.1
1.9
1.9
1.9
2.1
2.9
3.7
4.5
7.8
1.1
1.0
10.4
‘–F’ Speed
6.6
0.0
6.6
0.0
7.0
7.0
10.9
2.7
5.7
2.7
2.7
2.7
3.0
4.1
5.2
6.3
1.5
1.3
80
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns