CAT25C256K-TE13 ON Semiconductor, CAT25C256K-TE13 Datasheet - Page 8

• Manufacturer Part Number: CAT25C256K-TE13
• Manufacturer: ON Semiconductor

Specifications of CAT25C256K-TE13

• Density: 256Kb
• Interface Type: Serial (SPI)
• Organization: 32Kx8
• Access Time (max): 250ns
• Frequency (max): 3MHz
• Write Protection: Yes
• Data Retention: 100Year
• Operating Supply Voltage (typ): 3.3/5V
• Package Type: SOIC EIAJ
• Operating Temp Range: 0C to 70C
• Supply Current: 10mA
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (max): 6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Not Compliant

Doc. No. 25088-00 8/99 SPI-1
Figure 6. Write Instruction Timing
During an internal write cycle, all commands will be
ignored except the RDSR (Read Status Register) in-
struction.
The Status Register can be read to determine if the write
cycle is still in progress. If Bit 0 of the Status Register is
set at 1, write cycle is in progress. If Bit 0 is set at 0, the
device is ready for the next instruction
Page Write
The CAT25C128/256 features page write capability.
After the initial byte the host may continue to write up to
64 bytes of data to the CAT25C128/256. After each byte
of data is received, six lower order address bits are
internally incremented by one; the high order bits of
Figure 7. WRSR Timing
Note: Dashed Line= mode (1, 1) — — — —
Note: Dashed Line= mode (1, 1) — — — —
Note: Dashed Line= mode (1, 1) — — — —
Figure 8. Page Write Instruction Timing
SCK
CS
SO
SI
SO
SK
CS
SO
CS
SK
SI
SI
0
0
0
0
0
0
0
0
1
1
0
1
0
0
2
HIGH IMPEDANCE
2
HIGH IMPEDANCE
0
0
0
2
3
3
OPCODE
OPCODE
0
0
4
0
4
3
OPCODE
0
0
5
5
0
1
4
1
6
6
0
0
0
7
5
7
8
8
0
6
HIGH IMPEDANCE
ADDRESS
ADDRESS
1
21
7
21
8
MSB
22
22
8
7
address will remain constant.The only restriction is that
the 64 bytes must reside on the same page. If the
address counter reaches the end of the page and clock
continues, the counter will “roll over” to the first address
of the page and overwrite any data that may have been
written. The CAT25C128/256 is automatically returned
to the write disable state at the completion of the write
cycle. Figure 8 illustrates the page write sequence.
To write to the status register, the WRSR instruction
should be sent. Only Bit 2, Bit 3 and Bit 7 of the status
register can be written using the WRSR instruction.
Figure 7 illustrates the sequence of writing to status
register.
23
23 24-31 32-39
D7 D6 D5 D4 D3 D2 D1 D0
9
6
Data
Byte 1
24
10
25
5
Data
Byte 2
DATA IN
26
11
4
Data
Byte 3
DATA IN
DATA IN
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
27
12
3
28
29
7..1
Data Byte N
13
2
30
14
1
0
31
15
0