IS41LV16256-35K ISSI, Integrated Silicon Solution Inc, IS41LV16256-35K Datasheet - Page 9

• Manufacturer Part Number: IS41LV16256-35K
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: EDOr

Specifications of IS41LV16256-35K

• Organization: 256Kx16
• Density: 4Mb
• Address Bus: 9b
• Access Time (max): 35ns
• Maximum Clock Rate: Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: SOJ
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 220mA
• Pin Count: 40
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

IS41C16256
IS41LV16256
Notes:
10. Operation with the t
11. Operation within the t
12. Either t
13. t
14. t
15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both t
19. The I/Os are in open during READ cycles once t
20. The first χCAS edge to transition LOW.
21. The last χCAS edge to transition HIGH.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or
23. Last falling χCAS edge to first rising χCAS edge.
24. Last rising χCAS edge to next cycle’s last rising χCAS edge.
25. Last rising χCAS edge to first falling χCAS edge.
26. Each χCAS must meet minimum pulse width.
27. Last χCAS to go LOW.
28. I/Os controlled, regardless UCAS and LCAS.
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. K
10/28/05
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
2. V
3. In addition to meeting the transition rate specification, all input signals must transit between V
4. If CAS and RAS = V
5. If CAS = V
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that t
8. Assumes that t
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
operation is assured. The eight RAS cycles wake-up should be repeated any time the t
and V
a monotonic manner.
the amount that t
data output buffer, CAS and RAS must be pulsed for t
is greater than the specified t
is greater than the specified t
t
t
from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go
back to V
cycle.
LATE WRITE or READ-MODIFY-WRITE is not possible.
ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS
remains LOW and OE is taken back to LOW after t
READ-MODIFY-WRITE cycles.
OFF
WCS
WCS
RWD
IH
(MIN) and V
(MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to V
, t
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If t
(MIN), t
IL
RWD
RCH
(or between V
IH
, t
IL
) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled)
or t
, data output may contain data from the last valid READ cycle.
AWD
AWD
RRH
RCD
RCD
IL
and t
RCD
• t
(MAX) are reference levels for measuring timing of input signals. Transition times, are measured between V
must be satisfied for a READ cycle.
- t
AWD
• t
RCD
IH
exceeds the value shown.
RCD
CWD
RCD
RAD
IL
, data output is High-Z.
(MIN) and t
and V
(MAX) limit ensures that t
(MAX). If t
(MAX) limit ensures that t
(MAX).
are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If t
RAD
RCD
IH
) and assume to be 1 ns for all inputs.
(MAX) limit, access time is controlled exclusively by t
(MAX) limit, access time is controlled exclusively by t
CWD
RCD
is greater than the maximum recommended value shown in this table, t
• t
CWD
(MIN), the cycle is a READ-WRITE cycle and the data output will contain data read
OD
RAC
RCD
OEH
or t
(MAX) can be met. t
CP
(MAX) can be met. t
is met.
OFF
.
occur.
OD
and t
RCD
RAD
OEH
(MAX) is specified as a reference point only; if t
(MAX) is specified as a reference point only; if t
met (OE HIGH during WRITE cycle) in order to
AA
REF
CAC
.
.
refresh requirement is exceeded.
IH
and V
IL
(or between V
OH
RAC
or V
ISSI
will increase by
OL
IL
.
and V
WCS
RWD
IH
IH
RCD
) in
RAD
•
•
®
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