CY7C1297F-117AC Cypress Semiconductor Corp, CY7C1297F-117AC Datasheet - Page 5

• Manufacturer Part Number: CY7C1297F-117AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1297F-117AC

• Density: 1.125Mb
• Access Time (max): 7.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 117MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 16b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 220mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 18b
• Number Of Words: 64K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05429 Rev. *B
Interleaved Burst Address Table (MODE = Floating or V
ZZ Mode Electrical Characteristics
Truth Table
I
t
t
t
t
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Snooze Mode, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Notes:
DDZZ
ZZS
ZZREC
ZZI
RZZI
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BW
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Three-State when
Address
Parameter
BWE, GW = H.
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to three-state. OE is
a don't care for the remainder of the Write cycle.
OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW)
A1, A0
First
Cycle Description
00
01
10
11
[2, 3, 4, 5, 6]
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to snooze current
ZZ Inactive to exit snooze current
Address
Second
A1, A0
01
00
11
10
Address
External
External
External
External
External
Current
Used
None
None
None
None
None
None
Description
Next
Next
Next
Next
Next
Next
Address
A1, A0
Third
10
00
01
11
CE
H
X
X
X
X
H
H
X
H
X
L
L
L
L
L
L
L
L
1
Address
CE
Fourth
A1, A0
X
X
H
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
10
01
00
11
3
A
, BW
CE
DD
X
X
X
X
H
H
H
H
H
X
X
X
X
X
X
X
L
L
B
) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals (BW
2
)
ZZ ADSP
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Linear Burst Address Table (MODE = GND)
Address
Test Conditions
X
H
H
X
H
H
H
H
H
X
X
H
X
H
L
L
L
L
DD
DD
A
First
1
00
01
10
11
, A
– 0.2V
– 0.2V
0
ADSC
H
H
H
H
H
H
H
X
X
X
X
X
L
L
L
L
L
L
Address
Second
ADV
A
H
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
1
01
10
11
00
[A: B]
, A
0
. Writes may occur only on subsequent clocks
WRITE
X
X
X
X
X
X
X
H
H
H
H
H
H
H
X
L
L
L
2t
Min.
CYC
7
0
Address
A
Third
OE
1
10
00
01
11
H
H
H
H
X
X
X
X
X
X
L
X
L
L
L
X
X
L
, A
CY7C1297F
0
2t
2t
Max.
CLK
L-H Q
L-H Three-State
L-H D
L-H Q
L-H Three-State
L-H Q
L-H Three-State
L-H Q
L-H Three-State
L-H Q
40
L-H Three-State
L-H Three-State
L-H Three-State
L-H Three-State
L-H Three-State
L-H D
L-H D
CYC
CYC
X
Page 5 of 15
Three-State
Address
Fourth
A
1
00
01
10
11
DQ
, A
Unit
A
mA
ns
ns
ns
ns
, BW
0
B
),
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