CY7C1354BV25-166BZC Cypress Semiconductor Corp, CY7C1354BV25-166BZC Datasheet - Page 8

• Manufacturer Part Number: CY7C1354BV25-166BZC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1354BV25-166BZC

• Density: 9Mb
• Access Time (max): 3.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 166MHz
• Operating Supply Voltage (typ): 2.5V
• Address Bus: 18b
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 180mA
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 165
• Word Size: 36b
• Number Of Words: 256K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05292 Rev. *E
Because the CY7C1354BV25 and CY7C1356BV25 are
common I/O devices, data should not be driven into the device
while the outputs are active. The Output Enable (OE) can be
deasserted HIGH before presenting data to the DQ and DQP
(DQ
for CY7C1356BV25) inputs. Doing so will three-state the
output drivers. As a safety precaution, DQ and DQP (DQ
DQP
CY7C1356BV25) are automatically three-stated during the
data portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1354BV25/CY7C1356BV25 has an on-chip burst
counter that allows the user the ability to supply a single
address and conduct up to four WRITE operations without
reasserting the address inputs. ADV/LD must be driven LOW
in order to load the initial address, as described in the Single
Write Access section above. When ADV/LD is driven HIGH on
ZZ Mode Electrical Characteristics
Truth Table
I
t
t
t
t
Deselect Cycle
Continue Deselect Cycle
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
NOP/WRITE ABORT (Begin Burst) None
WRITE ABORT (Continue Burst)
IGNORE CLOCK EDGE (Stall)
SLEEP MODE
Notes:
DDZZ
ZZS
ZZREC
ZZI
RZZI
1. X = “Don't Care”, 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid
2. Write is defined by WE and BW
3. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = 1 inserts wait states.
6. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
OE is inactive or when the device is deselected, and DQs = data when OE is active
a,b,c,d
a,b,c,d
Parameter
/DQP
for CY7C1354BV25 and
Operation
[1, 2, 3, 4, 5, 6, 7]
a,b,c,d
for CY7C1354BV25 and DQ
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
[a:d]
. See Write Cycle Description table for details.
Description
None
None
External
Next
External
Next
External
Next
Next
Current
None
Address
Used
DQ
a,b
/DQP
CE ZZ
H
X
X
X
X
X
X
X
L
L
L
L
a,b
/DQP
a,b
H
a,b,c,d
L
L
L
L
L
L
L
L
L
L
L
for
a,b
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
ADV/LD
/
H
H
H
H
H
L
L
L
L
L
X
X
the subsequent clock rise, the chip enables (CE
CE
mented. The correct BW (BW
BW
cycle of the burst write in order to write the correct bytes of
data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
for the duration of t
DD
DD
3
a,b
− 0.2V
Test Conditions
− 0.2V
) and WE inputs are ignored and the burst counter is incre-
WE BWx
X
X
H
X
H
X
X
X
X
X
L
L
for CY7C1356BV25) inputs must be driven in each
X
X
X
X
X
X
H
H
X
X
L
L
L
L
H
H
X
X
X
X
X
X
X
X
ZZREC
OE
1
, CE
L
L
L
L
L
L
L
L
L
L
H
X
after the ZZ input returns LOW.
CEN CLK
2
, and CE
a,b,c,d
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
2t
Min.
CY7C1354BV25
CY7C1356BV25
CYC
0
for CY7C1354BV25 and
3
, must remain inactive
[a:d]
Data Out (Q)
Data Out (Q)
Three-State
Three-State
Three-State
Three-State
Three-State
Three-State
Three-State
2t
2t
Data In (D)
Data In (D)
Max
35
= Three-state when
CYC
CYC
Page 8 of 27
DQ
1
-
, CE
Unit
2
mA
ns
ns
ns
ns
, and
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