CY7C1354BV25-166BZC Cypress Semiconductor Corp, CY7C1354BV25-166BZC Datasheet
CY7C1354BV25-166BZC
Specifications of CY7C1354BV25-166BZC
Related parts for CY7C1354BV25-166BZC
CY7C1354BV25-166BZC Summary of contents
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... Document #: 38-05292 Rev. *E 256K x 36/512K x 18 Pipelined SRAM with Functional Description The CY7C1354BV25 and CY7C1356BV25 are 2.5V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states ...
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... D0 Q0 LOGIC ADV/LD C WRITE ADDRESS REGISTER 2 WRITE REGISTRY MEMORY AND DATA COHERENCY WRITE ARRAY CONTROL LOGIC DRIVERS INPUT E REGISTER 1 CY7C1354BV25-225 CY7C1354BV25-200 CY7C1356BV25-225 CY7C1356BV25-200 2.8 250 35 CY7C1354BV25 CY7C1356BV25 DQs DQP DQP INPUT E REGISTER 0 CY7C1354BV25-166 CY7C1356BV25-166 Unit 3.2 3.5 220 180 Page [+] Feedback ...
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... DQb DQa 18 63 DQa DQb DDQ 20 61 DDQ DQa DQb 22 59 DQa DQb 23 58 DQa DQPb 24 57 DQa DDQ 27 54 DDQ DQa DQa DQPa CY7C1354BV25 CY7C1356BV25 DDQ DQPa 74 DQa 73 DQa DDQ DQa 69 DQa DQa 63 DQa DDQ DQa 59 DQa DDQ ...
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... Pin Configurations (continued) CY7C1354BV25 (256K × 36) – 14 × 22 BGA DDQ DDQ DDQ DDQ DDQ CY7C1356BV25 (512K x 18)– BGA DDQ DDQ DDQ DDQ E(72 DDQ Document #: 38-05292 Rev. *E 119-ball BGA Pinout E(18 ADV/ DQP CLK CEN DQP MODE E(72 TMS TDI ...
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... Pin Configurations (continued) CY7C1354BV25 (256K × 36) – 13 × 15 fBGA E(288 CE2 C DQP DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ P NC E(72 MODE E(36) A CY7C1356BV25 (512K × 18) – 13 × 15 fBGA E(288 CE2 DDQ DDQ DDQ DDQ DDQ H NC ...
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... Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. Clock input to the JTAG circuitry. Power supply inputs to the core of the device. CY7C1354BV25 CY7C1356BV25 controls DQ and DQP , BW ...
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... During normal operation, this pin can be connected to Vss or left floating. Burst Read Accesses The CY7C1354BV25 and CY7C1356BV25 have an on-chip are burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs ...
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... CY7C1356BV25) are automatically three-stated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1354BV25/CY7C1356BV25 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four WRITE operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above ...
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... Address A[1:0] A[1:0] A[1: Partial Write Cycle Description Function (CY7C1354BV25) Read Write –No bytes written Write Byte a– (DQ and DQP a a) Write Byte b – (DQ and DQP b b) Write Bytes b, a Write Byte c – (DQ and DQP c c) Write Bytes c, a Write Bytes c, b Write Bytes Write Byte d – ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1354BV25/CY7C1356BV25 incorporates a serial boundary scan Test Access Port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance ...
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... TAP controller is not fully 1149.1-compliant. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR Document #: 38-05292 Rev. *E CY7C1354BV25 CY7C1356BV25 state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. ...
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... TEST-LOGIC 1 RESET 1 TEST-LOGIC/ 0 IDLE Note: 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05292 Rev SELECT DR-SCAN CAPTURE-DR CAPTURE-DR 0 SHIFT-DR 0 SHIFT- EXIT1-DR EXIT1- PAUSE-DR PAUSE- EXIT2-DR EXIT2-IR 1 UPDATE-DR UPDATE- CY7C1354BV25 CY7C1356BV25 1 SELECT IR-SCAN Page [+] Feedback ...
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... 2 100 µ GND ≤ V ≤ DDQ GND ≤ V ≤ DDQ [12, 13] Over the Operating Range Description (AC) > −0.5V for t < t /2. IL TCYC / ns CY7C1354BV25 CY7C1356BV25 Selection Circuitry TDO Min. Max. Unit 1.7 V 2.0 V 0.7 V 0 –0.3 0.7 V µA –30 30 µA – ...
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... TCK Test Mode Select TMS Test Data-In TDI Test Data-Out TDO Document #: 38-05292 Rev. *E [12, 13] Over the Operating Range (continued) Description 2. 1 TCYC t TMSS t TMSH t TDIS t TDIH t TDOV t TDOX CY7C1354BV25 CY7C1356BV25 Min. Max. Unit ALL INPUT PULSES 1.25V 1.5 ns Page [+] Feedback ...
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... Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document #: 38-05292 Rev. *E CY7C1356BV25 001 001 Reserved for version number. 01011001000010110 Reserved for future use. 00000110100 Allows unique identification of SRAM vendor Indicate the presence register. Bit Size Description CY7C1354BV25 CY7C1356BV25 Description Page [+] Feedback ...
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... Boundary Scan Exit Order (×36) Bit # 165-Ball B10 43 A10 44 C11 45 E10 46 F10 47 G10 48 D10 49 D11 50 E11 51 F11 G11 52 H11 53 J10 54 K10 55 L10 56 M10 57 J11 58 K11 59 L11 60 M11 61 N11 62 R11 63 R10 64 P10 CY7C1354BV25 CY7C1356BV25 (continued) 119-Ball ID 165-Ball Not Bonded Not Bonded (Preset to 1) (Preset ...
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... Not Bonded 59 (Preset to 0) Not Bonded 60 (Preset to 0) Not Bonded 61 (Preset R11 63 R10 64 P10 CY7C1354BV25 CY7C1356BV25 (continued) 119-Ball ID 165-Ball Not Bonded Not Bonded (Preset to 0) (Preset to 0) Not Bonded Not Bonded (Preset to 0) (Preset to 0) Not Bonded Not Bonded (Preset to 0) ...
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... MHz 2. 2.5V DD DDQ 5 7 /2), undershoot: V (AC)> -2V (Pulse width less than t CYC IL (min.) within 200ms. During this time V < V and CY7C1354BV25 CY7C1356BV25 Ambient Temperature DDQ 0°C to +70°C 2. –40°C to +85°C Min. Max. 2.375 2.625 2.375 V DD 2.0 0.4 1 ...
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... V DD and t is less than t to eliminate bus contention between SRAMs when sharing the same EOLZ CHZ CLZ CY7C1354BV25 CY7C1356BV25 [16] ALL INPUT PULSES 90% 90% 1.25V 10% 10% < 1.0 ns (c) fBGA Typ. ...
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... CLZ D(A1) D(A2) D(A2+1) Q(A3) BURST READ READ BURST WRITE Q(A3) Q(A4) READ D(A2+1) Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH,CE is HIGH CY7C1354BV25 CY7C1356BV25 -200 -166 Min. Max. Min. Max. Unit 1.5 1.5 ns 0.5 0.5 ns 0.5 0.5 ns 0.5 0.5 ns ...
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... The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle Document #: 38-05292 Rev. *E [23,24,26 D(A1) Q(A2) Q(A3) STALL READ WRITE STALL Q(A3) D(A4) DON’T CARE CY7C1354BV25 CY7C1356BV25 CHZ D(A4) Q(A5) NOP READ DESELECT CONTINUE Q(A5) DESELECT UNDEFINED Page ...
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... ZZ) Outputs (Q) Note: 27. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 28. I/Os are in High-Z when exiting ZZ sleep mode. Document #: 38-05292 Rev. *E CY7C1354BV25 CY7C1356BV25 t ZZREC t RZZI DESELECT or READ Only High-Z DON’T CARE ...
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... CY7C1354BV25-200BZI CY7C1356BV25-200BZI 166 CY7C1354BV25-166AC CY7C1356BV25-166AC CY7C1354BV25-166AI CY7C1356BV25-166AI CY7C1354BV25-166BGC CY7C1356BV25-166BGC CY7C1354BV25-166BGI CY7C1356BV25-166BGI CY7C1354BV25-166BZC CY7C1356BV25-166BZC 166 CY7C1354BV25-166BZI CY7C1356BV25-166BZI Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05292 Rev. *E Package Name Package Type A101 100-lead Thin Quad Flat Pack ( 1.4 mm) A101 100-lead Thin Quad Flat Pack ( ...
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... Package Diagrams 100-pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05292 Rev. *E CY7C1354BV25 CY7C1356BV25 51-85050-*A Page [+] Feedback ...
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... Package Diagrams (continued) Document #: 38-05292 Rev. *E 119-Lead BGA ( 2.4mm) BG119 CY7C1354BV25 CY7C1356BV25 51-85115-*B Page [+] Feedback ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 165-Ball FBGA ( 1.2 mm) BB165A CY7C1354BV25 CY7C1356BV25 51-85122-*C ...
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... Document History Page Document Title: CY7C1354BV25/CY7C1356BV25 256K x 36/512K x 18 Pipelined SRAM with NoBL™ Architecture Document Number: 38-05292 Orig. of REV. ECN No. Issue Date Change ** 114767 08/08/02 RCS *A 117938 08/20/02 RCS *B 126206 04/11/03 DPM *C 206704 See ECN NJY *D 239272 See ECN VBL ...