CY7C1069AV33-12ZC Cypress Semiconductor Corp, CY7C1069AV33-12ZC Datasheet - Page 5

• Manufacturer Part Number: CY7C1069AV33-12ZC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1069AV33-12ZC

• Density: 16Mb
• Access Time (max): 12ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 21b
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 260mA
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 54
• Word Size: 8b
• Number Of Words: 2M
• Lead Free Status / Rohs Status: Not Compliant

AC Switching Characteristics
Document #: 38-05255 Rev. *G
Notes
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
6. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
8. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. t
9. t
10. These parameters are guaranteed by design and are not tested.
11. The internal Write time of the memory is defined by the overlap of
12. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
power
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
minimum operating V
minimum operating V
I
is started.
from steady-state voltage.
a Write, and the transition of any of these signals can terminate the Write. The input data setup and hold timing should be referenced to the leading edge of
the signal that terminates the Write.
OL
HZOE
OUTPUT
Parameter
/I
OH
, t
HZCE
and transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise.
[10, 11]
, t
HZWE
Z 0 = 50Ω
and t
DD
DD
, normal SRAM operation can begin including reduction in V
, normal SRAM operation can begin including reduction in V
V
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
CE
CE
CE
CE
Write Cycle Time
CE
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
LZOE
CC
(a)
1
1
1
1
1
1
, t
(typical) to the First Access
LOW/CE
LOW/CE
HIGH/CE
LOW/CE
HIGH/CE
LOW/CE
LZCE
Rise time > 1V/ns
, and t
30 pF* *Capacitive Load consists of all
50Ω
2
2
2
2
LZWE
2
2
GND
3.3V
HIGH to Data Valid
HIGH to Low-Z
HIGH to Power Up
HIGH to Write End
LOW to High-Z
LOW to Power Down
Description
[9]
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV
Figure 3. AC Test Loads and Waveforms
components of the test environment
[ 9 ]
Over the Operating Range
V
TH
= 1.5V
[9]
CE
[ 9]
[8]
10%
1
LOW/CE
90%
[10]
All input pulses
[10]
2
(c)
HIGH
, and WE LOW. CE
DD
DD
[7]
to the data retention (V
to the data retention (V
power
Min
10
10
1
3
1
3
0
7
7
0
0
HZWE
time has to be provided initially before a Read/Write operation
–10
and t
90%
1
DD
DD
10%
and WE must be LOW along with CE
OUTPUT
Max
Fall time: > 1V/ns
SD
10
10
10
(3.0V). As soon as 1ms (T
(3.0V). As soon as 1ms (T
5
5
5
[5]
.
3.3V
*Including
jig and
scope
CCDR
CCDR
, 2.0V) voltage.
, 2.0V) voltage.
Min
12
12
5 pF*
1
3
1
3
0
8
8
0
0
R1 317 Ω
–12
(b)
CY7C1069AV33
power
power
Max
12
12
12
6
6
6
) after reaching the
) after reaching the
2
HIGH to initiate
351Ω
R2
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 5
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