UDA1341TS NXP Semiconductors, UDA1341TS Datasheet
UDA1341TS
Specifications of UDA1341TS
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UDA1341TS Summary of contents
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... DATA SHEET UDA1341TS Economy audio CODEC for MiniDisc (MD) home stereo and portable applications Product specification Supersedes data of 2001 Jun 29 INTEGRATED CIRCUITS 2002 May 16 ...
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... AC CHARACTERISTICS (DIGITAL) 13 APPLICATION INFORMATION 14 PACKAGE OUTLINE 15 SOLDERING 15.1 Introduction to soldering surface mount packages 15.2 Reflow soldering 15.3 Wave soldering 15.4 Manual soldering 15.5 Suitability of surface mount IC packages for wave and reflow soldering methods 16 DATA SHEET STATUS 17 DISCLAIMERS 2 Product specification UDA1341TS ...
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... MSB data output combined with LSB 16, 18 and 20 bits data input. The UDA1341TS has DSP features in playback mode like de-emphasis, volume, bass boost, treble and soft mute, which can be controlled via the L3-interface with a microcontroller ...
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... A-weighted A-weighted i stand-alone mode double differential mode 1 kHz 44.1 kHz −60 dB; A-weighted A-weighted i supply voltage = 3 V; note −60 dB; A-weighted code = 0; A-weighted 4 Product specification UDA1341TS MIN. TYP. MAX. UNIT 2.4 3.0 3.6 V 2.4 3.0 3.6 V 2.4 3.0 3.6 V − − 12.5 mA − ...
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... DIGITAL INTERFACE DSP FEATURES INTERPOLATION FILTER NOISE SHAPER DAC DAC 25 Fig.1 Block diagram ADCP V ADCN VINR2 PGA 4 0 dB/6 dB VINR1 SWITCH ADC1 22 AGCSTAT 9 OVERFL 13 L3MODE 14 L3-BUS L3CLOCK INTERFACE 15 L3DATA 12 SYSCLK PEAK DETECTOR 20 TEST1 21 TEST2 24 VOUTR 27 V SSA(DAC) MGR427 Product specification UDA1341TS ...
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... ADC and DAC reference voltage V SSA(ADC) V ref SSA(DAC) VINL1 DDA(ADC) 3 VOUTL 26 V DDA(DAC) VINR1 ADCN VOUTR 5 24 VINL2 23 QMUTE 6 V ADCP AGCSTAT 7 22 UDA1341TS VINR2 8 21 TEST2 OVERFL 9 20 TEST1 V DDD 10 19 DATAI V SSD DATAO 11 18 SYSCLK L3MODE BCK 13 16 L3CLOCK 14 15 L3DATA ...
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... The pins that are compatible with the UDA1340M are marked in Fig.3. 7.3 Analog front end The analog front end of the UDA1341TS consists of two stereo ADCs with a Programmable Gain Amplifier (PGA) in channel 2. The PGA is intended to pre-amplify a microphone signal applied to the input channel 2. ...
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... This noise shaping technique allows for high signal-to-noise ratios. The noise shaper output is converted into an analog signal using a filter stream digital-to-analog converter. 8 Product specification UDA1341TS Interpolation filter (DAC) to 128f s ITEM CONDITIONS 0 to 0.45f s > ...
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... MSB data output with LSB 16 bits input. Left and right data-channel words are time multiplexed. The formats are illustrated in Fig.4. The UDA1341TS allows for double speed data monitoring purposes. In this case the sound features bass boost, treble and de-emphasis cannot be used. However, volume control and soft-mute can still be controlled ...
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WS LEFT >= BCK DATA MSB B2 LSB WS LEFT >= BCK DATA MSB B2 LSB MSB WS LEFT 16 BCK DATA MSB WS LEFT BCK DATA MSB B2 ...
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... The maximum input clock and data rate is 64f All transfers are byte-wise, i.e. they are based on groups of 8 bits. Data will be stored in the UDA1341TS after the eighth bit of a byte has been received. A multibyte transfer is illustrated in Fig.7. ...
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... AGC time constant and AGC output level 0 1 DATA1 peak level value read-out (information from UDA1341TS to microcontroller STATUS reset, system clock frequency, data input format, DC-filter, input gain switch, output gain switch, polarity control, double speed and power control ...
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... L3DATA 2002 May 16 t CLK(L3)L T cy(CLK)L3 t CLK(L3)H t h(L3)DA t su(L3)DA BIT 0 PL0 PL1 PL2 PL3 Fig.6 Timing for data transfer mode. t stp(L3) address data byte #1 data byte #2 Fig.7 Multibyte transfer. 13 Product specification UDA1341TS t stp(L3) t h(L3)D t h(L3)DA BIT 7 PL4 PL5 MGR430 address MGR432 ...
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... The other bits in the data byte (bits bits represent the value that is placed in the selected registers. For the UDA1341TS the following modes can be selected: • STATUS In this mode the features reset, system clock frequency, ...
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... A 3-bit value to select the data input format. Table 10 Data input format settings IF2 IF1 IF0 Product specification UDA1341TS REGISTER SELECTED Data input format FUNCTION S-bus 1 LSB-justified 16 bits 0 LSB-justified 18 bits 1 LSB-justified 20 bits 0 MSB-justified 1 LSB-justified 16 bits input and MSB-justified output 0 LSB-justified 18 bits input and ...
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... Power control A 2-bit value to disable the ADC and/or DAC to reduce power consumption. The default setting is given in Table 5. Table 16 Power control settings PC1 PC0 ADC 0 0 off 0 1 off Product specification UDA1341TS FUNCTION DAC off on off on ...
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... The default setting is given in Table 5. Table 19 Bass boost settings VOLUME VC0 (dB) BB3 BB2 BB1 BB0 − − − − − −∞ −∞ Product specification UDA1341TS REGISTER SELECTED Bass boost BASS BOOST FLAT MIN. (dB) (dB ...
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... A 2-bit value to program the mode of the sound processing filters of bass boost and treble. The default setting is given Table Table 24 Mode filter switch settings FUNCTION FUNCTION 18 Mute MT FUNCTION 0 no mute 1 mute Mode M1 M0 FUNCTION 0 0 flat 0 1 minimum 1 0 minimum 1 1 maximum Product specification UDA1341TS ...
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... AGC control is enabled and not in the double differential mode. The default setting is given in Table 5. Table 27 MIC sensitivity settings MS2 MS1 MS0 MIXER GAIN 1 (dB −1.5 −3.0 : −43.5 −45.0 −∞ 19 Product specification UDA1341TS REGISTER SELECTED MIC sensitivity MIC AMPLIFIER GAIN (dB) − + +21 ...
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... Table 32 AGC time constant settings AT2 (dB FS) 20 Input channel 2 amplifier gain AGC time constant ATTACK TIME AT1 AT0 (ms Product specification UDA1341TS INPUT CHANNEL 2 AMPLIFIER GAIN (dB) −3.0 0 −2.5 1 −2.0 0 −1.5 1 −1.0 0 −0 0 59.5 0 60.0 1 60.5 DECAY TIME (ms) 100 100 200 200 200 400 400 400 ...
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... For peak data <010100, the error is larger due to limited bit length. 2002 May 16 PL0 peak level value (6 bits) PL3 PL2 × 11 log 2 ------------------------- - < Product specification UDA1341TS READ-OUT DATA PL1 PL0 −∞ n. n.a. −90 n.a. −84. note note −2. −1.48 1 ...
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... L CONDITIONS note 1 note 1 note 1 operation mode ADC power-down operation mode DAC power-down operation mode DAC power-down ADC power-down 22 Product specification UDA1341TS = all voltages measured with DDD DDA MIN. MAX. − 5.0 − 150 −65 +125 −20 +85 − ...
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... N)/S < 0.1% note 2 with respect to V SSA ) must be connected to the same external power supply unit Product specification UDA1341TS MIN. TYP. MAX. − 0. 0.5 V DDD DDD −0.5 − 0.2V DDD − ...
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... Product specification UDA1341TS MIN. TYP. MAX. − − 1.0 − − 0.1 − −85 −80 − −37 − ...
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... A-weighted − − code = 0; A-weighted − − kHz; ripple V = 100 mV ripple(p-p) 25 Product specification UDA1341TS MIN. TYP. MAX. − tbf −37 − − tbf − tbf − tbf − tbf − 900 − 0.1 − ...
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... MHz sys ≥ 19.2 MHz f sys MSB-justified format addressing mode addressing mode data transfer mode data transfer mode data transfer and addressing mode data transfer and addressing mode 26 Product specification UDA1341TS MIN. TYP. MAX 131 − 0.30T 0.70T sys sys − ...
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... CWH handbook, full pagewidth T sys handbook, full pagewidth WS t BCK( BCK T cy DATAO DATAI 2002 May 16 t CWL Fig.8 System clock timing. t h; d(DATO)(WS) t BCK(L) Fig.9 Serial interface timing. 27 Product specification UDA1341TS MGL443 t d(DATO)(BCK) t h;DATO t s;DATI t h;DATI MGG840 ...
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... V ref 28 C22 100 nF ( VOUTL 26 47 μF ( VOUTR 24 47 μF (16 V) QMUTE 23 AGCSTAT 22 TEST2 21 TEST1 DDA(DAC) R29 1 Ω V DDA MGR433 Product specification UDA1341TS C3 47 μF (16 V) R23 left output 100 Ω R22 10 kΩ R26 right output 100 Ω R27 10 kΩ ...
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... 0.38 0.20 10.4 5.4 7.9 0.65 0.25 0.09 10.0 5.2 7.6 REFERENCES JEDEC JEITA MO-150 detail 1.03 0.9 1.25 0.2 0.13 0.63 0.7 EUROPEAN PROJECTION Product specification UDA1341TS SOT341 θ (1) θ 1.1 8 0.1 o 0.7 0 ISSUE DATE 99-12-27 03-02-19 ...
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... Use a low voltage ( less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 °C. 30 Product specification UDA1341TS ...
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... Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2002 May 16 (1) not suitable not suitable suitable not recommended not recommended 31 Product specification UDA1341TS SOLDERING METHOD WAVE REFLOW suitable (3) suitable suitable (4)(5) suitable (6) ...
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... NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. 32 Product specification UDA1341TS DEFINITION ...
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... NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 33 Product specification UDA1341TS ...
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... Interface, Security and Digital Processing expertise Customer notification This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for package outline drawings which were updated to the latest version. ...