TB28F008SC-100 Intel, TB28F008SC-100 Datasheet - Page 7

• Manufacturer Part Number: TB28F008SC-100
• Manufacturer: Intel

Specifications of TB28F008SC-100

• Density: 8Mb
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: -40C to 85C
• Package Type: SOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

A
DQ
CE#
RP#
OE#
0
PRELIMINARY
–A
Sym
0
–DQ
20
7
OUTPUT
INPUT/
INPUT
INPUT
INPUT
INPUT
4-Mbit: A - A
8-Mbit: A - A
16-Mbit: A - A
Type
0
0
0
18
19
20
,
,
ADDRESS INPUTS: Inputs for addresses during read and write operations.
Addresses are internally latched during a write cycle.
DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles;
outputs data during memory array, status register, and identifier code read cycles.
Data pins float to high-impedance when the chip is deselected or outputs are
disabled. Data is internally latched during a write cycle.
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and
sense amplifiers. CE#-high deselects the device and reduces power consumption to
standby levels.
RESET/DEEP POWER-DOWN: When driven low, RP# inhibits write operations
which provides data protection during power transitions, puts the device in deep
power-down mode, and resets internal automation. RP#-high enables normal
operation. Exit from deep power-down sets the device to read array mode.
RP# at V
lock-bits when the master lock-bit is set. RP# = V
thereby enabling block erase and program operations to locked memory blocks.
Block erase, program, or lock-bit configuration with V
spurious results and should not be attempted.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
Address
Address
Counter
Buffer
Input
Latch
HH
Decoder
Decoder
16 Mbit
enables setting of the master lock-bit and enables configuration of block
4 Mbit
8 Mbit
X
Y
Table 2. Pin Descriptions
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
Figure 1. Block Diagram
Output
Buffer
16-Mbit: Thirty-Two
A
A
A
64-Kbyte Blocks
8-Mbit: Sixteen
0
0
0
Comparator
4-Mbit: Eight
–A
Y Gating
–A
–A
DQ - DQ
Identifier
Register
Register
Status
Data
0
20
18
19
Name and Function
7
Buffer
Input
Write State
Command
Register
Machine
HH
overrides block lock-bits,
IH
Program/Erase
Voltage Switch
I/O Logic
< RP# < V
CE#
WE#
OE#
RP#
RY/BY#
V
V
GND
V
PP
CC
CC
HH
produce
7