TB28F008SC-100 Intel, TB28F008SC-100 Datasheet - Page 32

• Manufacturer Part Number: TB28F008SC-100
• Manufacturer: Intel

Specifications of TB28F008SC-100

• Density: 8Mb
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: -40C to 85C
• Package Type: SOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
6.4
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal V
2. I
3. Includes RY/BY#.
4. Block erases, programs, and lock-bit configurations are inhibited when V
5. Automatic Power Savings (APS) reduces typical I
6. CMOS inputs are either V
7. Sampled, not 100% tested.
8. Master lock-bit set operations are inhibited when RP# = V
9. RP# connection to a V
32
V
V
V
V
V
V
V
V
V
V
V
Sym
IL
IH
OL
OH1
OH2
PPLK
PPH1
PPH2
PPH3
LKO
HH
valid for all product versions (packages and speeds).
current is the sum of I
between V
above V
master lock-bit is set and RP# = V
and RP# = V
attempted with V
CCWS
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage (TTL)
Output High Voltage
(CMOS)
V
V
V
V
V
RP# Unlock Voltage
and I
PP
PP
PP
PP
CC
DC Characteristics—Commercial Temperature
PPH3
Lockout Voltage
Voltage
Voltage
Voltage
Lockout Voltage
PPLK
CCES
(max).
IH
Parameter
. Block erase, program, and lock-bit configuration operations are not guaranteed and should not be
(max) and V
are specified with the device de-selected. If read or written while in erase suspend mode, the device’s
IH
< RP# < V
CCWS
HH
supply is allowed for a maximum cumulative period of 80 hours.
CC
or I
PPH1
± 0.2 V or GND ± 0.2 V. TTL inputs are either V
HH
CCES
.
(min), between V
Notes Min Max Min Max Min Max Unit
IH
3,7
3,7
3,7
4,7
8,9
and I
. Block erases and programs are inhibited when the corresponding block-lock bit is set
7
7
CCR
2.7 V V
–0.5 0.8 –0.5 0.8 –0.5 0.8
0.85
V
V
–0.4
2.0 V
2.4
2.0
CC
CC
or I
+ 0.5
CCW
0.4
1.5
CC
CC
PPH1
CCR
.
3.3 V V
0.85
V
V
–0.4
11.4 12.6 11.4 12.6
11.4 12.6 11.4 12.6
to 1 mA at 5 V and 3 mA at 2.7 V and 3.3 V V
2.0 V
2.4
3.0
4.5
2.0
(max) and V
CC
CC
IH
+ 0.5
. Block lock-bit configuration operations are inhibited when the
0.4
1.5
3.6
5.5
CC
CC
0.85
V
V
–0.4
2.0 V
2.4
4.5
2.0
5 V V
CC
CC
PPH2
+ 0.5
0.45
CC
1.5
5.5
(min), between V
CC
PP
CC
IL
V
V
V
V V
V V
V V
V V
V
V
V
V
V Set Master Lock-Bit
or V
PPLK
voltage and T
(Continued)
I
I
I
I
Override Lock-Bit
OL
OH
OH
OH
IH
, and not guaranteed in the range
CC
CC
CC
CC
.
= 2 mA (2.7V, 3.3V)
= –2.5 mA
= –2.5 mA
= –100 µA
= V
= V
= V
= V
5.8 mA (5V)
PPH2
CC
CC
CC
CC
A
PRELIMINARY
(max) and V
Min
Min
Min
Min
= +25 C. These currents are
Conditions
CC
Test
in static operation.
PPH3
(min), and