AM29DL800BB-70WBI Spansion Inc., AM29DL800BB-70WBI Datasheet - Page 20

• Manufacturer Part Number: AM29DL800BB-70WBI
• Manufacturer: Spansion Inc.

Specifications of AM29DL800BB-70WBI

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: FBGA
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Supply Current: 12mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

Note: See Table 5 for program command sequence.
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 5 shows
the address and data requirements for the chip erase
command sequence.
When the Embedded Erase algorithm is complete, that
bank returns to reading array data and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. Refer to the Write Operation Status section for
information on these status bits.
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that
18
Increment Address
Figure 3. Program Operation
Embedded
in progress
algorithm
Program
No
Command Sequence
Write Program
Last Address?
Programming
from System
Verify Data?
Completed
Data Poll
START
Yes
Yes
D A T A
No
Am29DL800B
S H E E T
occurs, the chip erase command sequence should be
reinitiated once that bank has returned to reading array
data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations tables
in the AC Characteristics section for parameters, and
Figure 18 section for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two
additional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Table 5 shows the address
and data requirements for the sector erase command
sequence.
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands within the bank may be written. Loading the
sector erase buffer may be done in any sequence, and
the number of sectors may be from one sector to all
sectors. The time between these additional cycles must
be less than 50 µs, otherwise the last address and
command may not be accepted, and erasure may be-
gin. It is recommended that processor interrupts be
disabled during this time to ensure all commands are
accepted. The interrupts can be re-enabled after the
last Sector Erase command is written. Any command
other than Sector Erase or Erase Suspend during
the time-out period resets that bank to reading
array data. The system must rewrite the command se-
quence and any additional addresses and commands.
The system can monitor DQ3 (in the erasing bank) to
determine if the sector erase timer has timed out (See
the section on DQ3: Sector Erase Timer.). The time-out
begins from the rising edge of the final WE# pulse in
the command sequence.
When the Embedded Erase algorithm is complete, the
bank returns to reading array data and addresses are
no longer latched. Note that while the Embedded Erase
operation is in progress, the system can read data from
the non-erasing bank. The system can determine the
status of the erase operation by reading DQ7, DQ6,
DQ2, or RY/BY# in the erasing bank. Refer to the Write
Operation Status section for information on these sta-
tus bits.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. However, note that a hardware reset im-
21519C5 March 17, 2009