AM29DL800BB-70WBI Spansion Inc., AM29DL800BB-70WBI Datasheet
AM29DL800BB-70WBI
Specifications of AM29DL800BB-70WBI
Related parts for AM29DL800BB-70WBI
AM29DL800BB-70WBI Summary of contents
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Am29DL800B Data Sheet (Retired Product) This product has been retired and is not recommended for designs. For new and current designs please contact your Spansion representative for alternates. Availability of this document is retained for reference and historical purposes only. ...
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This page left intentionally blank Am29DL800B 21519_C5 March 17, 2009 ...
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... Am29DL800B 8 Megabit ( 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory This product has been retired and is not recommended for designs. For new and current designs please contact your Spansion representative for alternates. Availability of this document is retained for reference and historical purposes only. ...
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... GENERAL DESCRIPTION The Am29DL800B Mbit, 3.0 volt-only flash memory device, organized as 524,288 words or 1,048,576 bytes. The device is offered in 44-pin SO, 48-pin TSOP, and 48-ball FBGA packages. The word- wide (x16) data appears on DQ0–DQ15; the byte-wide (x8) data appears on DQ0–DQ7. This device requires only a single 3 ...
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... Standby Mode ........................................................................ 10 Automatic Sleep Mode ........................................................... 10 RESET#: Hardware Reset Pin ............................................... 11 Output Disable Mode .............................................................. 11 Table 2. Am29DL800BT Top Boot Sector Architecture ..................12 Table 3. Am29DL800BB Bottom Boot Sector Architecture .............13 Autoselect Mode ..................................................................... 13 Table 4. Am29DL800B Autoselect Codes (High Voltage Method) ..14 Sector Protection/Unprotection ............................................... 14 Temporary Sector Unprotect .................................................. 14 Figure 1. Temporary Sector Unprotect Operation........................... 14 Figure 2 ...
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PRODUCT SELECTOR GUIDE Family Part Number Speed Option Full Voltage Range: V Max Access Time (ns) CE# Access (ns) OE# Access (ns) Note: See “AC Characteristics” for full specifications. BLOCK DIAGRAM A0–A18 RY/BY# A0–A18 STATE RESET# ...
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CONNECTION DIAGRAMS A15 1 2 A14 A13 3 A12 4 A11 5 A10 WE# 11 RESET RY/BY# 15 A18 16 A17 ...
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... NC DQ2 DQ10 DQ0 DQ8 CE# Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compro- mised if the package body is exposed to temperatures above 150°C for prolonged periods of time. Am29DL800B 44 RESET A10 39 A11 38 A12 ...
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PIN DESCRIPTION A0-A18 = 19 Addresses DQ0-DQ14 = 15 Data Inputs/Outputs DQ15/A-1 = DQ15 (Data Input/Output, word mode), A-1 (LSB Address Input, byte mode) CE# = Chip Enable OE# = Output Enable WE# = Write Enable BYTE# = Selects 8-bit ...
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... SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector Valid Combinations for FBGA Packages Order Number AM29DL800BT70, AM29DL800BB70 AM29DL800BT90, AM29DL800BB90 AM29DL800BT120, AM29DL800BB120 Am29DL800B Package Marking WBC, WBI, D800BT70V WBD, D800BB70V D, F WBF WBC, ...
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DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register it- self does not occupy any addressable memor y location. The register is a ...
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... DC Characteristics table represents the CC3 standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed ...
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... V ±0.3 V, the standby current will greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash March 17, 2009 21519C5 memory, enabling the system to read the boot-up firm- ware from the Flash memory. ...
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Table 2. Sector Address Bank Address Bank Sector A18 A17 A16 SA0 SA1 SA2 SA3 SA4 SA5 SA6 Bank ...
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... When using programming equipment, the autoselect mode requires V (11 12 address pin ID A9. Address pins A6, A1, and A0 must be as shown in March 17, 2009 21519C5 Am29DL800BB Bottom Boot Sector Architecture Sector Size (Kbytes/ A15 A14 A13 A12 Kwords ...
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... V on address pin A9 and OE#. ID This method is compatible with programmer routines written for earlier 3.0 volt-only AMD flash devices. Pub- lication number 21467 contains further details; contact an AMD representative to request a copy. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD’ ...
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START PLSCNT = 1 RESET Wait 1 μs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with ...
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Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 5 for com- mand definitions). In addition, the following hardware data protection measures prevent accidental erasure or ...
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Table 5 shows the address and data requirements. This method is an alternative to that shown in Table 4, which is intended for PROM programmers and requires V on address pin ...
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Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Increment Address Last Address? Programming Completed Note: See Table 5 for program command sequence. Figure 3. Program Operation Chip Erase Command Sequence Chip erase ...
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If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 4 illustrates the algorithm for the erase opera- tion. Refer ...
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Command Definitions Table 5. Am29DL800B Command Definitions Command Sequence (Note 1) Addr Data Addr Data Read (Note 6) 1 Reset (Note 7) 1 Word Manufacturer ID 4 Byte Word Device ID, 4 Top Boot Block Byte Word Device ID, 4 ...
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WRITE OPERATION STATUS The device provides several bits to determine the sta- tus of a write operation in the bank where a program or erase operation is in progress: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 6 and the ...
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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since ...
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The remaining scenario is that the system initially de- termines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, de- termining the ...
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Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Erase Suspended Sector Erase-Suspend- Erase Read Suspend Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied ...
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DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description I Input Load Current Input Load Current LIT I Output Leakage Current LO V Active Read Current CC I CC1 (Notes Active Write Current CC I ...
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... DC CHARACTERISTICS Zero-Power Flash 500 1000 Note: Addresses are switching at 1 MHz Figure 9. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 Note °C March 17, 2009 21519C5 1500 2000 2500 Time Frequency in MHz Figure 10. Typical I vs. Frequency CC1 Am29DL800B 3000 3500 4000 3 ...
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TEST CONDITIONS Device Under Test C L 6.2 kΩ Note: Diodes are IN3064 or equivalent Figure 11. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted 3.0 V 1.5 V Input 0.0 V Figure 12. Input Waveforms ...
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AC CHARACTERISTICS Read-Only Operations Parameter JEDEC Std Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV Output Enable to Output ...
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AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low (NOT During Embedded t Ready Algorithms) to Read Mode (See Note) t RESET# Pulse Width RP ...
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AC CHARACTERISTICS Word/Byte Configuration (BYTE#) Parameter JEDEC Std Description t t CE# to BYTE# Switching Low or High ELFL/ ELFH t BYTE# Switching Low to Output HIGH Z FLQZ t BYTE# Switching High to Output Active FHQV CE# OE# BYTE# ...
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AC CHARACTERISTICS Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS t Address Setup Time to OE# low during toggle bit polling ASO t t ...
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AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE# OE# WE Data RY/BY VCS Notes program address program data Illustration shows device in word ...
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AC CHARACTERISTICS t WC Valid PA Addresses t AH CE# OE WE# t WPH t DS Valid Data In WE# Controlled Write Cycle Figure 19. Back-to-Back Read/Write Cycle Timings t RC Addresses VA t ACC t CE CE# ...
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AC CHARACTERISTICS Addresses CE# t OEH WE# OE Valid Data DQ6/DQ2 RY/BY# Note Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read ...
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AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std t V Rise and Fall Time (See Note) VIDR ID RESET# Setup Time for Temporary Sector t RSP Unprotect RESET# Hold Time from RY/BY# High for t RRB Temporary Sector Unprotect Note: ...
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AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time ELAX Data Setup Time DVEH ...
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AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation ...
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ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Program Time Word Program Time Byte Mode Chip Program Time (Note 3) Word Mode Notes: 1. Typical program and erase times assume the following conditions: 25 programming typicals ...
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PHYSICAL DIMENSIONS TS 048—48-Pin Standard TSOP * For reference only. BSC is an ANSI standard for Basic Space Centering Am29DL800B Dwg rev AA; 10/99 21519C5 March 17, 2009 ...
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PHYSICAL DIMENSIONS (continued) FBB048 —48-Ball Fine-Pitch Ball Grid Array (FBGA package March 17, 2009 21519C5 Am29DL800B Dwg rev AF; 10/99 41 ...
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PHYSICAL DIMENSIONS (continued) SO 044—44-Pin Small Outline Am29DL800B Dwg rev AC; 10/99 21519C5 March 17, 2009 ...
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REVISION SUMMARY Revision A (January 1998) Initial release. Revision A+1 (January 1998) Reset Command Deleted last paragraph in section, which applied to RESET#, not the reset command. Revision A+2 (Febrauary 1998) Hardware Reset (RESET#) Added note to table, fixed references ...
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... Copyright ©2002-2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trade- marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Copyright © 2006-2009 Spansion Inc. All rights reserved. Spansion ™ ™ ...