M30624FGMFP Renesas Electronics America, M30624FGMFP Datasheet - Page 17

• Manufacturer Part Number: M30624FGMFP
• Manufacturer: Renesas Electronics America

Specifications of M30624FGMFP

• Cpu Family: M16C
• Device Core Size: 16/32Bit
• Frequency (max): 10MHz
• Interface Type: UART
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 20KB
• # I/os (max): 87
• Number Of Timers - General Purpose: 11
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 10-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Timing
16
Switching characteristics (referenced to V
85
Table 1.26.22. Memory expansion and microprocessor modes
Note 1: Calculated according to the BCLK frequency as follows:
Note 3: Specify a product of –40°C to 85°C to use it.
Note 2: This is standard value shows the timing when the output is off,
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
d(BCLK-AD)
h(BCLK-AD)
d(BCLK-CS)
h(BCLK-CS)
d(BCLK-RD)
h(BCLK-RD)
d(BCLK-WR)
h(BCLK-WR)
d(BCLK-DB)
h(BCLK-DB)
h(RD-AD)
h(WR-AD)
d(DB-WR)
h(WR-DB)
d(BCLK-ALE)
h(BCLK-ALE)
Symbol
o
C (Note 3), CM15 = “1” unless otherwise specified)
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
by a circuit of the right figure.
For example, when V
of output “L” level is
td(DB – WR) =
Address output delay time
Address output hold time (BCLK standard)
Chip select output hold time (BCLK standard)
ALE signal output hold time
RD signal output hold time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (WR standard)(Note2)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip select output delay time
ALE signal output delay time
RD signal output delay time
WR signal output delay time
Data output hold time (BCLK standard)
Data output delay time (WR standard)
(when accessing external memory area with wait)
t = –CR X ln (1 – V
t = – 30pF X 1k
= 6.7ns.
f(BCLK)
Parameter
10
OL
9
= 0.2V
X ln (1 – 0.2V
OL
– 80
/ V
CC
CC
, C = 30pF, R = 1k , hold time
)
CC
[ns]
CC
= 3V, V
/ V
CC
SS
)
Measuring condition
= 0V at Topr = – 20
Figure 1.31.1
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(Note1)
Min.
– 4
Standard
4
0
0
4
0
0
4
0
o
C to 85
Max.
DBi
60
60
60
60
60
80
o
Mitsubishi microcomputers
(Low voltage version)
C / – 40
M16C / 62M Group
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
o
C to
C
R