HEF4051BT,652 NXP Semiconductors, HEF4051BT,652 Datasheet - Page 12

IC MUX/DEMUX 8X1 16SOIC

HEF4051BT,652

Manufacturer Part Number
HEF4051BT,652
Description
IC MUX/DEMUX 8X1 16SOIC
Manufacturer
NXP Semiconductors
Series
4000Br
Type
Analog Multiplexerr
Datasheet

Specifications of HEF4051BT,652

Package / Case
16-SOIC (0.154", 3.90mm Width)
Function
Multiplexer/Demultiplexer
Circuit
1 x 8:1
On-state Resistance
175 Ohm
Voltage Supply Source
Single, Dual Supply
Voltage - Supply, Single/dual (±)
3 V ~ 15 V, ±15 V
Current - Supply
80µA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Number Of Channels
1 Channel
On Resistance (max)
2500 Ohm @ 5 V
On Time (max)
280 ns @ 5 V
Off Time (max)
290 ns @ 5 V
Supply Voltage (max)
15 V
Supply Voltage (min)
3 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Switches
Single
Multiplexer Configuration
Single 8:1
Number Of Inputs
8
Number Of Outputs
1
Analog Switch On Resistance
2500@5VOhm
Package Type
SO
Power Supply Requirement
Single
Single Supply Voltage (min)
3V
Single Supply Voltage (typ)
5/9/12V
Single Supply Voltage (max)
15V
Dual Supply Voltage (min)
Not RequiredV
Dual Supply Voltage (typ)
Not RequiredV
Dual Supply Voltage (max)
Not RequiredV
Mounting
Surface Mount
Pin Count
16
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-3979-5
933372940652
HEF4051BTD
HEF4051BTD
NXP Semiconductors
Table 10.
[1]
HEF4051B_9
Product data sheet
Input
Yn, Z
V
Fig 16. Test circuit for measuring switching times
DD
For Yn to Z or Z to Yn propagation delays use V
or V
EE
Test data is given in
Definitions:
DUT = Device Under Test.
R
C
R
T
L
L
Test data
Sn and E
V
= Load capacitance including test jig and probe.
= Load resistance.
= Termination resistance should be equal to output impedance Z
DD
or V
SS
t
≤ 20 ns
r
, t
Table
f
10.
GENERATOR
V
0.5V
negative
positive
M
PULSE
pulse
pulse
DD
All information provided in this document is subject to legal disclaimers.
0 V
0 V
V
V
I
I
EE
Load
C
50 pF
. For Sn to Yn or Z propagation delays use V
90 %
10 %
L
V I
Rev. 09 — 25 March 2010
t
t
f
r
R T
V
V
V
M
M
90 %
DD
10 %
DUT
R
10 kΩ
L
V
I
t
t
W
W
V O
S1 position
t
V
PHL
o
DD
C L
of the pulse generator.
V
V
8-channel analog multiplexer/demultiplexer
R L
[1]
M
M
or V
t
t
r
f
S1
EE
V
001aaj903
t
V
DD
PLH
EE
open
V
V
SS
EE
DD
.
t
V
PZH
EE
, t
PHZ
HEF4051B
© NXP B.V. 2010. All rights reserved.
t
V
PZL
DD
, t
PLZ
other
V
12 of 23
EE

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