AD9887AKS-140 Analog Devices Inc, AD9887AKS-140 Datasheet - Page 25

• Manufacturer Part Number: AD9887AKS-140
• Description: IC INTRFACE ANALOG/DVI 160-MQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9887AKS-140

• Rohs Status: RoHS non-compliant
• Applications: Graphic Cards, VGA Interfaces
• Interface: Analog and Digital
• Voltage - Supply: 3.15 V ~ 3.45 V
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount

2-Wire Serial Register Map
The AD9887 is initialized and controlled by a set of registers, which determine the operating modes. An external controller is
employed to write and read the Control Registers through the 2-line serial interface port.
Hex
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
Read and
Write or
Read Only
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits
7:0
7:0
7:4
7:2
7:3
7:0
7:0
7:0
7:0
7:0
7:0
7:1
7:1
7:1
7:3
01101001
1101
10000
10000000
10000000
00100000
10000000
10000000
10000000
Default
Value
1
1000000
1000000
1000000
1
01
1
0
001
0
0
Register
Name
Chip Revision
PLL Div MSB This register is for Bits [11:4] of the PLL divider. Larger values mean
PLL Div LSB
VCO/CPMP
Phase Adjust
Clamp
Placement
Clamp
Duration
Hsync Output
Pulsewidth
Red Gain
Green Gain
Blue Gain
Red Offset
Green Offset
Blue Offset
Mode
Control 1
Table IX. Control Register Map
Bits 7 through 4 represent functional revisions to the analog interface.
Bit 7—Must be set to 1 for proper device operation.
ADC Clock phase adjustment. Larger values mean more delay.
Number of clock periods that the Clamp signal is actively clamping.
Sets the number of pixel clocks that HSOUT will remain active.
Controls ADC input range (Contrast) of each respective channel.
Bit 7—Channel Mode. Determines Single Channel or Dual Channel
Function
Bits 3 through 0 represent nonfunctional related revisions.
Revision 0 = 0000 0000
the PLL operates at a faster rate. This register should be loaded first
whenever a change is needed. (This will give the PLL more time to
lock.) See Note 1.
Bits [7:4] LSBs of the PLL divider word. See Note 1.
Bits [6:5] VCO Range. Selects VCO frequency range. (See PLL
description.)
Bits [4:2] Charge Pump Current. Varies the current that drives the
low-pass filter. (See PLL description.)
(1 LSB = T/32)
Places the Clamp signal an integer number of clock periods after the trail-
ing edge of the Hsync signal.
Bigger values give less contrast.
Controls dc offset (Brightness) of each respective channel. Bigger
values decrease brightness.
Output Mode. (Logic 0 = Single Channel Mode, Logic 1 = Dual
Channel Mode.)
Bit 6—Output Mode. Determine Interleaved or Parallel Output Mode.
(Logic 0 = Interleaved Mode, Logic 1 = Parallel Mode.)
Bit 5—OUTPHASE. Determines which port outputs the first data byte
after Hsync. (Logic 0 = B Port, Logic 1 = A Port.)
Bit 4—Hsync Output polarity. (Logic 0 = Logic High Sync, Logic 1 =
Logic Low Sync.)
Bit 3—Vsync Output Invert. (Logic 0 = Invert, Logic 1 = No Invert.)
AD9887