LTC4310IMS-2#PBF Linear Technology, LTC4310IMS-2#PBF Datasheet - Page 11

• Manufacturer Part Number: LTC4310IMS-2#PBF
• Description: IC I2C ISOLATOR SMBUS 10MSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap I²C Isolatorsr

Specifications of LTC4310IMS-2#PBF

• Tx/rx Type: I²C Logic
• Capacitance - Input: 10pF
• Voltage - Supply: 3 V ~ 5.5 V
• Current - Supply: 7mA
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time: -

applicaTions inForMaTion
Bus Rising Edge Waveform
When all external pull-downs on SCL1 (Figure 1) turn off,
the SCL1 rising waveform will resemble that shown in
Figure 4. The LTC4310-1 senses that SCL1 is rising and
transmits a message to the other LTC4310-1 to release
SCL2 high. During the transmission, the first LTC4310-1
also drives SCL1 to 0.35V, so that when the transmission
is complete, both buses will rise simultaneously from
0.35V at a rate of (0.35 • V
minimizes the effective skew between the two buses. When
SCL1 reaches 0.35 • V
rise rate regulation circuitry. The bus then rises with a
time constant of (R
at which point the I
current is activated.
Figure 5 shows SCL1 and SCL2 for an entire 100kHz
switching cycle. Because the LTC4310-1 regulates the bus
rise rate to (0.35 • V
more quickly than the 3.3V bus signal. Both buses reach
(0.35 • V
between the buses is nearly zero. The LTC4310-2 functions
the same as the LTC4310-1, except the controlled rise rate
is limited to (0.35 • V
1V/DIV
CC
) in approximately 900ns, so the effective skew
Figure 4. SCL1 Rising Waveform of SCL1
for Application Circuit Shown in Figure 1
SCL1 SET TO 0.35V
DURING TX
BUS
BOOST
CC
CC
CC
• C
RISE TIME
ACCELERATOR
ACTIVE
)/900ns, the 5V bus signal rises
)/300ns.
, the LTC4310-1 deactivates its
BUS
200ns/DIV
dV/dt =
rise time accelerator pull-up
CC
) until it reaches 0.45 • V
)/900ns. This functionality
0.35 • V
900 ns
CC
BUS RC
431012 F04
CC
,
Start-Up, Data and Clock Hot Swap Circuitry
The LTC4310 contains power-on reset (POR) circuitry that
sets the data and clock pins in a high impedance state and
deactivates the transmit circuitry until the EN voltage is
high, the device is not in thermal shutdown and the V
voltage is above 2.4V. After the LTC4310 exits the POR
state, it activates its transmit circuitry and communicates
its SDA, SCL logic states across the barrier to the other
LTC4310 via its TXP and TXN pins.
The receive circuitry remains deactivated for an additional
900µs after the LTC4310 exits POR. The 900µs filter time is
required for the LTC4310 to charge its RXP and RXN pins
to their DC bias voltage, assuming a 0.01µF common-mode
noise filtering capacitor at the center-tap of the secondary
side of the external transformer. When the filter time has
elapsed, the LTC4310 activates its receive circuitry and
decodes the messages it receives on its RXP and RXN
pins, registering the logic state of the remote I
When both the local and remote two-wire buses are “quiet”
(i.e., no data transactions are occurring on either bus), the
LTC4310 then drives its READY pin low to indicate that it
has linked the logic state of the local I
state of the remote I
will now drive its SDA and SCL pins to the logic state of the
remote I
on RXP and RXN. The LTC4310 considers a two-wire bus
1V/DIV
2
C bus, as specified by the messages it receives
LTC4310-1/LTC4310-2
Figure 5. 100kHz SCL Waveforms for
Application Circuit Shown in Figure 1
SCL2
SCL1
2
C bus. This means that the LTC4310
2µs/DIV
2
C bus with the logic
431012 F05
2
C bus.

431012f
CC