MAX9249GCM/V+T Maxim Integrated Products, MAX9249GCM/V+T Datasheet - Page 28

• Manufacturer Part Number: MAX9249GCM/V+T
• Description: IC SERIALIZER GMSL LVDS 48TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX9249GCM/V+T

• Function: Serializer
• Data Rate: 2.5Gbs
• Input Type: LVDS
• Output Type: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Outputs: -
• Number Of Inputs: -

Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Usually the microcontroller is either on the serializer
(MAX9249) side for video-display applications or on the
deserializer side for image-sensing applications. For the
former case, both the CDS pins of the MAX9249/GMSL
deserializer are set to low, and for the latter case, the
CDS pins are set to high. However, if the CDS pin of the
MAX9249 is low and the same pin of the GMSL dese-
rializer is high, then the MAX9249/GMSL deserializer
connect to both FCs simultaneously. In such a case, the
FCs on either side can communicate with the MAX9249/
GMSL deserializer.
Contentions of the control link can happen if the FCs
on both sides are using the link at the same time. The
MAX9249/GMSL deserializer do not provide the solution
for contention avoidance. The serializer/deserializer do
not send an acknowledge frame when communication
fails due to contention. Users can always implement a
higher layer protocol to avoid the contention. In addi-
tion, if UART communication across the serial link is not
required, the FCs can disable the forward and reverse
control channel through the REVCCEN and FWDCCEN
bits (0x04 D[1:0]) in the MAX9249/GMSL deserializer.
UART communication across the serial link is stopped
and contention between FCs no longer occurs. During
dual FCs operation, if one of the CDS pins on either side
changes state, the link resumes the corresponding state
described in the Link Startup Procedure section.
As an example of dual FC use in an image-sensing appli-
cation, the MAX9249 can be in sleep mode and waiting
for wake-up by the GMSL deserializer. After wake-up, the
serializer-side FC sets the MAX9249 CDS pin low and
assumes master control of the MAX9249 registers.
In some applications, the input clock to the MAX9249
(RXCLKIN_) includes jitter that reduces link reliability.
The MAX9249 has a programmable narrow-band jitter-
filtering PLL to attenuate frequency components outside
the PLL’s bandwidth (< 100kHz, typ). Enable the jitter-
filtering PLL by setting DISFPLL = 0 (0x05 D6).
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Microcontrollers on Both Sides of the
GMSL Link (Dual µC Control)
Jitter-Filtering PLL
Both the video clock rate (f
channel clock rate (f
to support applications with multiple clock speeds. It is
recommended to enable the serial link after RXCLKIN_
stabilizes. Stop RXCLKIN_ for 5Fs and restart the serial
link or toggle SEREN after each change in the RXCLKIN_
frequency to recalibrate any automatic settings if a clean
frequency change cannot be guaranteed. The reverse
control channel remains unavailable for 350Fs after serial
link start or stop. Limit on-the-fly changes in f
tors of less than 3.5 at a time to ensure that the device
recognizes the UART sync pattern. For example, when
lowering the UART frequency from 1Mbps to 100kbps,
first send data at 333kbps and then at 100kbps to have
reduction ratios of 3 and 3.333, respectively.
For quick loss-of-lock notification, the GMSL deserializer
can loop back its LOCK output to the MAX9249 using
the INT signal. Connect the LOCK output to the INT
input of the GMSL deserializer. The interrupt output on
the MAX9249 follows the transitions at the LOCK output
of the GMSL deserializer. Reverse control-channel com-
munication does not require an active forward link to
operate and accurately tracks the LOCK status of the
video link. LOCK asserts for video link only and not for
the configuration link.
The line-fault detector in the MAX9249 monitors for line
failures such as short to ground, short to power supply,
and open link for system fault diagnosis. Figure 3 shows
the required external resistor connections. LFLT = low
when a line fault is detected and LFLT = high when the
line returns to normal. The line-fault type is stored in
0x08 D[3:0] of the MAX9249. The fault-detector thresh-
old voltages are referenced to the MAX9249 ground.
Additional passive components set the DC level of the
cable (Figure 3). If the MAX9249 and GMSL deserializer
grounds are different, the link DC voltage during normal
operation can vary and cross one of the fault-detection
thresholds. For the fault-detection circuit, select the
resistor’s power rating to handle a short to the battery
and use surface-mount resistors with small case size to
minimize parasitic effects to the high-speed signal. Table
10 lists the mapping for line-fault types.
Changing the Clock Frequency
UART
LOCK Output Loopback
) can be changed on-the-fly
RXCLKIN_
Line-Fault Detection
) and the control-
UART
to fac-