MAX9249GCM/V+T Maxim Integrated Products, MAX9249GCM/V+T Datasheet - Page 19

• Manufacturer Part Number: MAX9249GCM/V+T
• Description: IC SERIALIZER GMSL LVDS 48TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX9249GCM/V+T

• Function: Serializer
• Data Rate: 2.5Gbs
• Input Type: LVDS
• Output Type: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Outputs: -
• Number Of Inputs: -

Figure 16. 4-Channel Mode Serial Link Data Format
Table 3. Maximum Audio WS Frequency (kHz) for Various RXCLKIN_ Frequencies
The I
from 8kHz to 192kHz and audio word lengths from 4 bits
to 32 bits. The audio bit clock (SCK) does not have to
be synchronized with RXCLKIN_. The MAX9249 auto-
matically encodes audio data into a single bit stream
synchronous with RXCLKIN_. The GMSL deserializer
decodes the audio stream and stores audio words in a
FIFO. Audio rate detection uses an internal oscillator to
continuously determine the audio data rate and output
the audio in I
default. When the audio channel is disabled, the audio
data on the MAX9249 and GMSL deserializer is treated
as a control pin (CNTL0).
Low RXCLKIN_ frequencies limit the maximum audio
sampling rate. Table 3 lists the maximum audio sam-
pling rate for various RXCLKIN_ frequencies. Spread-
WORD LENGTH
2
S audio channel supports audio sampling rates
*DIN27 FROM LVDS DATA (RXIN3_) OR EXTERNAL PIN (CNTL1).
NOTE: LOCATIONS OF THE LVDS RGB DATA AND CONTROL SIGNALS
(BITS)
DIN0
R0
16
18
20
24
32
8
ARE SET ACCORDING TO THE VESA STANDARD PANEL BITMAP.
2
S format. The audio channel is enabled by
DIN1
R1
______________________________________________________________________________________
Serializer with LVDS System Interface
(RXIN[2:0]_)
> 192
> 192
185.5
174.6
152.2
123.7
12.5
LVDS
DATA
DIN17
B5
RXCLKIN_ FREQUENCY
DIN18 DIN19 DIN20
HS
Audio Channel
> 192
> 192
> 192
> 192
182.7
148.4
15
(DRS = LOW)
VS
Gigabit Multimedia Serial Link
(MHz)
DE
> 192
> 192
> 192
> 192
> 192
164.3
16.6
DIN21
R6
32 BITS
DIN22
R7
spectrum settings do not affect the I
clock frequency.
The control channel is available for the FC to send
and receive control data over the serial link simultane-
ously with the high-speed data. Configuring the CDS pin
allows the FC to control the link from either the MAX9249
or the GMSL deserializer side to support video-display or
image-sensing applications.
The control channel between the FC and MAX9249 or
GMSL deserializer runs in base mode or bypass mode
according to the mode selection (MS) input of the device
connected to the FC. Base mode is a half-duplex control
channel and the bypass mode is a full-duplex control
channel. In base mode, the FC is the host and can
access the registers of both the MAX9249 and GMSL
deserializer from either side of the link by using the GMSL
DIN23
> 192
> 192
> 192
> 192
> 192
> 192
Control Channel and Register Programming
> 20
G6
(RXIN3_)
DIN24
LVDS
DATA
G7
DIN25 DIN26 DIN27 DIN28
B6
> 192
> 192
185.5
174.6
152.2
123.7
6.25
B7
RES/CNTL1
RXCLKIN_ FREQUENCY
> 192
> 192
> 192
> 192
182.7
148.4
7.5
(DRS = HIGH)
CNTL2
CHANNEL/CNTL0
(MHz)
AUDIO
ACB
BIT
CHANNEL BIT
> 192
> 192
> 192
> 192
> 192
164.3
CONTROL-
FORWARD
8.33
2
FCC
S data rate or WS
CHECK BIT
PACKET
PARITY
PCB
> 192
> 192
> 192
> 192
> 192
> 192
> 10
19