CYV15G0104TRB-BGXC Cypress Semiconductor Corp, CYV15G0104TRB-BGXC Datasheet
CYV15G0104TRB-BGXC
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CYV15G0104TRB-BGXC Summary of contents
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... CYV15G0104TRB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility (data and BIST) with other HOTLink devices. The transmit (TX) channel of the CYV15G0104TRB HOTLink II device accepts scrambled 10-bit transmission characters. These characters are serialized and output from ...
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... CYV15G0104TRB Serializer and Reclocking Deserializer Logic Block Diagram Document Number : 38-02100 Rev. *D The CYV15G0104TRB is ideal for SMPTE applications where different data rates and serial interface standards are necessary for each channel ...
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... Clock Multiplier Character-Rate Clock TXBISTB PABRSTB RXRATEA RXPLLPDA TRGRATEA TXRATEB TXCKSELB PABRSTB SDASEL[2..1]A[1:0] TOE[2..1]B ROE[2..1]A RXBISTA[1:0] TXBISTB CYV15G0104TRB RESET TRST JTAG TMS Boundary TCLK Scan TDI Controller TDO LFIA 10 10 RXDA[9:0] BISTSTA 2 RXCLKA+ RXCLKA– ROE[2..1]A ROUTA1+ ROUTA1– ...
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... ADDR REF NC GND GND GND GND [0] CLKB– REF RE NC GND NC GND GND CLKB+ CLKOA ADDR ADDR RX REPDO NC GND GND [2] [1] CLKA GND NC GND GND CLKOB CLKA– CYV15G0104TRB ROUT A2– A2– IN ROUT A2+ A2+ SPD LDTD TRST TDO NC V GND CC SELB ...
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... REF ADDR GND GND GND GND GND CLKB– [0] RE REF GND GND GND NC GND CLKOA CLKB+ REPDO RX ADDR ADDR GND GND GND A CLKA+ [1] [ GND GND GND NC GND CLKA– CLKOB CYV15G0104TRB TOUT B1– TOUT B1+ TMS TDI ULCA INSELA RESET ...
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... Pin Definitions CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer Name I/O Characteristics Signal Description Transmit Path Data and Status Signals TXDB[9:0] LVTTL Input, Transmit Data Inputs. TXDB[9:0] data inputs are captured on the rising edge of the synchronous, transmit interface clock. The transmit interface clock is selected by the TXCKSELB latch sampled by via the device configuration interface ...
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... Pin Definitions (continued) CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer Name I/O Characteristics Signal Description BISTSTA LVTTL Output, BIST Status Output. When RXBISTA[1:0] = 10, BISTSTA (along with RXDA[1:0]) synchronous to the displays the status of the BIST reception. See RXCLKA ± output each combination of BISTSTA and RXDA[1:0]. ...
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... Pin Definitions (continued) CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer Name I/O Characteristics Signal Description ULCA LVTTL Input, Use Local Clock. When ULCA is LOW, the RXPLL is forced to lock to TRGCLKA± instead internal pull-up of the received serial data stream. While ULCA is LOW, the link fault indicator LFIA is LOW indicating a link fault ...
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... Pin Definitions (continued) CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer Name I/O Characteristics Signal Description [6] TXCKSELB Internal Latch Transmit Clock Select. [6] TXRATEB Internal Latch Transmit PLL Clock Rate Select. [6] TRGRATEA Internal Latch Reclocker Output PLL Clock Rate Select. [6] RXPLLPDA Internal Latch Receive Channel Power Control. ...
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... TXCLKOB. The clock multiplier PLL can accept a REFCLKB± input between 19.5 MHz and 150 MHz, however, this clock range is limited by the operating mode of the CYV15G0104TRB clock multiplier (TXRATEB) and by the level on the SPDSELB input. [4] ...
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... CYV15G0104TRB Receive Data Path Serial Line Receivers Two differential Line Receivers, INA1± and INA2±, are available on the receive channel for accepting serial data streams ...
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... Each driver can be enabled or disabled separately via the device configuration interface. When a driver is disabled via the configuration interface internally powered down to reduce device power. If both reclocker serial drivers are in this disabled state, the internal CYV15G0104TRB ÷ 10) or ÷ 20) training clock from the ...
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... Device Reset State When the CYV15G0104TRB is reset by assertion of RESET, all state machines, counters, and configuration latches in the device are initialized to a reset state. Additionally, the JTAG controller must also be reset for valid operation (even if JTAG testing is not performed). See “ ...
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... Transmit Input Register. When TXCKSELB = 1, the input register TXDB[9:0] is clocked by REFCLKB In this mode, the phase alignment buffer in the transmit path is bypassed. When TXCKSELB = 0, TXCLKB is used to clock in the input register TXDB[9:0]. Document Number : 38-02100 Rev. *D CYV15G0104TRB Page [+] Feedback ...
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... (111b) Document Number : 38-02100 Rev. *D DATA5 DATA4 DATA3 SDASEL1A[1] SDASEL1A[0] RXBISTA[0] X INTERNAL TEST REGISTERS DO NOT WRITE TO THESE ADDRESSES TXBISTB CYV15G0104TRB Reset DATA2 DATA1 DATA0 Value 0 0 RXRATEA 1011111 X X TRGRATEA 1010110 ROE2A ROE1A X 1011001 1011111 0 TXCKSELB TXRATEB 1010110 TOE2B TOE1B ...
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... Reset the Phase Alignment Buffer. [Optional if phase align buffer is bypassed.] JTAG Support The CYV15G0104TRB contains a JTAG port to allow system level diagnosis of device interconnect. Of the available JTAG modes, boundary scan, and bypass are supported. This capability is present only on the LVTTL inputs and outputs, the TRGCLKA± ...
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... Monitor Data Received {BISTSTA, RXDA[0], RXDA[1]} = BIST_START (101) Start of BIST Detected Compare Next Character Match End-of-BIST State Yes, {BISTSTA, RXDA[0], RXDA[1]} = BIST_LAST_GOOD (010) BIST_ERROR (110) CYV15G0104TRB Receive BIST Detected LOW RX PLL Out of Lock {BISTSTA, RXDA[0], RXDA[1]} = BIST_DATA_COMPARE (000, 001) No Page [+] Feedback ...
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... Document Number : 38-02100 Rev. *D Static Discharge Voltage.......................................... > 2000 V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Power-up Requirements The CYV15G0104TRB requires one power supply. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Operating Range + 0.5V CC ...
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... CYV15G0104TRB DC Electrical Characteristics Parameter Description Differential CML Serial Outputs: OUTA1, OUTA2, OUTB1, OUTB2OUTC1, OUTC2, OUTD1, OUTD2 V Output HIGH Voltage OHC (V Referenced Output LOW Voltage OLC (V Referenced Output Differential Voltage ODIF |(OUT+) (OUT)| Differential Serial Line Receiver Inputs: INA1 ...
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... CYV15G0104TRB AC Electrical Characteristics Parameter CYV15G0104TRB Transmitter LVTTL Switching Characteristics Over the Operating Range f TXCLKB Clock Cycle Frequency TS t TXCLKB Period=1/f TXCLK [16] t TXCLKB HIGH Time TXCLKH [16] t TXCLKB LOW Time TXCLKL [16, 17, 18, 19] t TXCLKB Rise Time TXCLKR [16, 17, 18, 19] t TXCLKB Fall Time TXCLKF Transmit Data Set-up Time to ...
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... JTAG Test Clock Period TCLK CYV15G0104TRB Device RESET Characteristics Over the Operating Range t Device RESET Pulse Width RST CYV15G0104TRB Transmitter and Reclocker Serial Output Characteristics Over the Operating Range Parameter t Bit Time B [16] t CML Output Rise Time 2080% (CML Test Load) ...
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... CYV15G0104TRB AC Electrical Characteristics Parameter Notes 23. The duty cycle specification is a simultaneous condition with the t cycle cannot be as large as 30%–70%. 24. TRGCLKA± has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time. TRGCLKA± must be within 1500 PPM (0.15%) of the transmitter PLL reference (REFCLK±) frequency. Although transmitting to a HOTLink II receiver channel necessitates the frequency difference between the transmitter and receiver reference clocks to be within ± ...
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... Reclocker Jitter Generation - SD Data Rate JRGENSD [16, 26] t Reclocker Jitter Generation - HD Data Rate JRGENHD CYV15G0104TRB Receive PLL Characteristics Over the Operating Range t Receive PLL lock to input data stream (cold start) RXLOCK Receive PLL lock to input data stream t Receive PLL Unlock Rate RXUNLOCK ...
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... CYV15G0104TRB HOTLink II Transmitter Switching Waveforms Transmit Interface Write Timing REFCLKB selected TXRATEB = 1 REFCLKB TXDB[ 9 :0] Transmit Interface TXCLKOB Timing TXRATE = 1 REFCLKB Note 29 TXCLKOB (internal) Transmit Interface TXCLKOB Timing t TXRATEB = 0 REFCLKB Note29 TXCLKOB Notes 27. When REFCLKB± is configured for half-rate operation (TXRATEB = 1) and data is captured using REFCLKB instead of a TXCLKB clock. Data is captured using both the rising and falling edges of REFCLKB. 28. The TXCLKOB output remains at the character rate regardless of the state of TXRATEB and does not follow the duty cycle of REFCLKB± ...
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... Switching Waveforms for the CYV15G0104TRB HOTLink II Receiver Receive Interface Read Timing RXRATEA = 0 RXCLKA+ RXCLKA– RXDA[9:0] Receive Interface Read Timing RXRATEA = 1 RXCLKA+ RXCLKA– RXDA[9:0] Bus Configuration Write Timing ADDR[2:0] DATA[6:0] WREN Document Number : 38-02100 Rev RXCLKP t RXDV– t RXDV+ t RXCLKP t RXDV– ...
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... VCC POWER E03 VCC POWER E04 VCC POWER E17 VCC POWER E18 VCC POWER E19 VCC POWER E20 VCC POWER CYV15G0104TRB Ball Signal Name Signal Type ID F17 VCC POWER F18 NC NO CONNECT F19 NC NO CONNECT F20 NC NO CONNECT G01 GND GROUND ...
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... V16 VCC POWER V17 RXDA[9] LVTTL OUT V18 RXDA[5] LVTTL OUT V19 RXDA[2] LVTTL OUT V20 RXDA[1] LVTTL OUT W01 TXDB[5] LVTTL IN CYV15G0104TRB Ball Signal Name Signal Type ID L19 NC NO CONNECT L20 GND GROUND M01 NC NO CONNECT M02 NC NO CONNECT W03 ...
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... Table 7. Package Coordinate Signal Allocation (continued) Ball Signal Name Signal Type ID U02 TXDB[1] LVTTL IN Document Number : 38-02100 Rev. *D Ball Signal Name Signal Type ID W02 TXDB[7] LVTTL IN CYV15G0104TRB Ball Signal Name Signal Type ID Page [+] Feedback ...
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... Ordering Information Speed Ordering Code Standard CYV15G0104TRB-BGXC Package Diagram Figure 3. 256-Lead L2 Ball Grid Array ( 1.57 mm) BL256 HOTLink is a registered trademark and HOTLink trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document Number : 38-02100 Rev. *D ...
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... Document History Page Document Title: CYV15G0104TRB Independent Clock HOTLink II™ Serializer and Reclocking Deserializer Document Number: 38-02100 ISSUE REV. ECN NO. DATE ** 244348 See ECN *A 338721 See ECN *B 384307 See ECN *C 1034021 See ECN *D 2897032 03/19/10 Document Number : 38-02100 Rev. *D © Cypress Semiconductor Corporation, 2002-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product ...