AD9806KST Analog Devices Inc, AD9806KST Datasheet - Page 7

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AD9806KST

Manufacturer Part Number
AD9806KST
Description
IC CCD SIGNAL PROC 10BIT 48-LQFP
Manufacturer
Analog Devices Inc
Type
CCD Signal Processor, 10-Bitr
Datasheet

Specifications of AD9806KST

Rohs Status
RoHS non-compliant
Input Type
Logic
Output Type
Logic
Interface
3-Wire Serial
Mounting Type
Surface Mount
Package / Case
48-LQFP
Analog Front End Type
CCD
Analog Front End Category
Video
Interface Type
Serial (3-Wire)
Input Voltage Range
0.5V
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Resolution
10b
Number Of Adc's
1
Power Supply Type
Analog/Digital
Operating Temp Range
-20C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Number Of Channels
1
Current - Supply
-
Lead Free Status / RoHS Status
Not Compliant

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TIMING SPECIFICATIONS
ADCCLK
ADCCLK
D0–D9
SIGNAL
CLPDM
CLPOB
VIDEO
D0–D9
INPUT
CCD
SHD
SHP
PBLK
CCD
NOTES:
1. SHP AND SHD SHOULD BE OPTIMALLY ALIGNED WITH THE CCD SIGNAL. SAMPLES ARE TAKEN AT THE RISING EDGES.
2. ADCCLK RISING EDGE MUST OCCUR AT LEAST 15ns AFTER THE RISING EDGE OF SHP (
3. RECOMMENDED PLACEMENT FOR ADCCLK RISING EDGE IS BETWEEN THE RISING EDGE OF SHD AND FALLING EDGE OF SHP.
4. OUTPUT LATENCY IS 9 CYCLES.
5. ACTIVE LOW CLOCK PULSE MODE IS SHOWN.
EFFECTIVE
PIXELS
NOTES:
1. CLPOB PULSEWIDTH SHOULD BE A MINIMUM OF 10 OB PIXELS WIDE, 20 OB PIXELS ARE RECOMMENDED.
2. CLPDM PULSEWIDTH SHOULD BE AT LEAST 1 s WIDE.
3. PBLK IS NOT REQUIRED, BUT RECOMMENDED IF THE CCD SIGNAL AMPLITUDE EXCEEDS 1V p-p.
4. CLPDM OVERWRITES PBLK.
5. ACTIVE LOW CLAMP PULSE MODE IS SHOWN.
N–0
t
N
INHIBIT
t
OD
N
t
HOLD
N–9
N+1
NOTE:
EXAMPLE OF OUTPUT DATA LATCHED BY ADCCLK RISING EDGE.
t
OD
N–9
t
HOLD
t
ID
OPTICAL BLACK
N+1
N–8
t
ID
N+2
t
ID
N–8
N+2
BLANKING
INTERVAL
N–7
ADCCLK RISING EDGE PLACEMENT
N+3
N–7
N–6
N+3
DUMMY BLACK
t
N+4
INHIBIT
).
N–5
N–6
N+5
N+4
EFFECTIVE
PIXELS
N–5
AD9806

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